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69646a28e6
Summary: This patch fixes pr23772 [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80". The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable. To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP). Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations. When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant ) It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt). Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb Reviewed By: efriedma Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70680
75 lines
2.1 KiB
LLVM
75 lines
2.1 KiB
LLVM
; pr23772 - [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80"
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; RUN: llc -march=thumb -mcpu=cortex-m3 -O3 -filetype=asm -o - %s | FileCheck %s
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; CHECK-NOT: sub{{.*}} sp, r{{.*}}, #
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; CHECK: .fnend
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; TODO: Missed optimization. The three instructions generated to subtract SP can be converged to a single one
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32"
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target triple = "thumbv7m-unknown-unknown"
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%B = type {%B*}
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%R = type {i32}
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%U = type {%U*, i8, i8}
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%E = type {%B*, %U*}
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%X = type {i32, i8, i8}
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declare external [0 x i8]* @memalloc(i32, i32, i32)
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declare external void @memfree([0 x i8]*, i32, i32)
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define void @foo(%B* %pb$, %R* %pr$) nounwind {
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L.0:
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%pb = alloca %B*
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%pr = alloca %R*
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store %B* %pb$, %B** %pb
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store %R* %pr$, %R** %pr
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%pe = alloca %E*
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%0 = load %B*, %B** %pb
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%1 = bitcast %B* %0 to %E*
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store %E* %1, %E** %pe
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%2 = load %R*, %R** %pr
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%3 = getelementptr %R, %R* %2, i32 0, i32 0
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%4 = load i32, i32* %3
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switch i32 %4, label %L.1 [
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i32 1, label %L.3
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]
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L.3:
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%px = alloca %X*
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%5 = load %R*, %R** %pr
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%6 = bitcast %R* %5 to %X*
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store %X* %6, %X** %px
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%7 = load %X*, %X** %px
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%8 = getelementptr %X, %X* %7, i32 0, i32 0
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%9 = load i32, i32* %8
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%10 = icmp ne i32 %9, 0
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br i1 %10, label %L.5, label %L.4
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L.5:
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%pu = alloca %U*
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%11 = call [0 x i8]* @memalloc(i32 8, i32 4, i32 0)
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%12 = bitcast [0 x i8]* %11 to %U*
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store %U* %12, %U** %pu
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%13 = load %X*, %X** %px
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%14 = getelementptr %X, %X* %13, i32 0, i32 1
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%15 = load i8, i8* %14
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%16 = load %U*, %U** %pu
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%17 = getelementptr %U, %U* %16, i32 0, i32 1
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store i8 %15, i8* %17
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%18 = load %E*, %E** %pe
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%19 = getelementptr %E, %E* %18, i32 0, i32 1
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%20 = load %U*, %U** %19
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%21 = load %U*, %U** %pu
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%22 = getelementptr %U, %U* %21, i32 0, i32 0
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store %U* %20, %U** %22
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%23 = load %U*, %U** %pu
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%24 = load %E*, %E** %pe
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%25 = getelementptr %E, %E* %24, i32 0, i32 1
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store %U* %23, %U** %25
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br label %L.4
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L.4:
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%26 = load %X*, %X** %px
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%27 = bitcast %X* %26 to [0 x i8]*
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call void @memfree([0 x i8]* %27, i32 8, i32 0)
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br label %L.2
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L.1:
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br label %L.2
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L.2:
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br label %return
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return:
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ret void
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}
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