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f65ec601b0
Fix the ARM backend's analyzeBranch so it doesn't ignore predicated return instructions, and make the MachineVerifier rule more strict. Differential Revision: https://reviews.llvm.org/D40061
178 lines
5.7 KiB
LLVM
178 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc %s -mtriple=thumbv6m-arm-none-eabi -o - -asm-verbose=false | FileCheck %s --check-prefix=CHECK-V6M
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; RUN: llc %s -mtriple=thumbv7m-arm-none-eabi -o - -asm-verbose=false | FileCheck %s --check-prefix=CHECK-V7M
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define i32 @test_values(i32 %a, i32 %b) minsize optsize {
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; CHECK-V6M-LABEL: test_values:
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; CHECK-V6M: mov r2, r0
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; CHECK-V6M-NEXT: ldr r0, .LCPI0_0
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; CHECK-V6M-NEXT: cmp r2, #50
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; CHECK-V6M-NEXT: beq .LBB0_5
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; CHECK-V6M-NEXT: cmp r2, #1
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; CHECK-V6M-NEXT: beq .LBB0_7
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; CHECK-V6M-NEXT: cmp r2, #30
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; CHECK-V6M-NEXT: beq .LBB0_8
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; CHECK-V6M-NEXT: cmp r2, #0
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; CHECK-V6M-NEXT: bne .LBB0_6
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; CHECK-V6M-NEXT: adds r0, r1, r0
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; CHECK-V6M-NEXT: bx lr
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; CHECK-V6M-NEXT: .LBB0_5:
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; CHECK-V6M-NEXT: adds r0, r0, r1
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; CHECK-V6M-NEXT: adds r0, r0, #4
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; CHECK-V6M-NEXT: .LBB0_6:
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; CHECK-V6M-NEXT: bx lr
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; CHECK-V6M-NEXT: .LBB0_7:
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; CHECK-V6M-NEXT: adds r0, r0, r1
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; CHECK-V6M-NEXT: adds r0, r0, #1
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; CHECK-V6M-NEXT: bx lr
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; CHECK-V6M-NEXT: .LBB0_8:
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; CHECK-V6M-NEXT: adds r0, r0, r1
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; CHECK-V6M-NEXT: adds r0, r0, #2
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; CHECK-V6M-NEXT: bx lr
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; CHECK-V6M-NEXT: .p2align 2
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; CHECK-V6M-NEXT: .LCPI0_0:
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; CHECK-V6M-NEXT: .long 537923600
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;
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; CHECK-V7M-LABEL: test_values:
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; CHECK-V7M: mov r2, r0
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; CHECK-V7M-NEXT: ldr r0, .LCPI0_0
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; CHECK-V7M-NEXT: cmp r2, #50
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; CHECK-V7M-NEXT: beq .LBB0_5
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; CHECK-V7M-NEXT: cmp r2, #1
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; CHECK-V7M-NEXT: beq .LBB0_7
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; CHECK-V7M-NEXT: cmp r2, #30
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; CHECK-V7M-NEXT: beq .LBB0_8
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; CHECK-V7M-NEXT: cbnz r2, .LBB0_6
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; CHECK-V7M-NEXT: add r0, r1
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; CHECK-V7M-NEXT: bx lr
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; CHECK-V7M-NEXT: .LBB0_5:
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; CHECK-V7M-NEXT: add r0, r1
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; CHECK-V7M-NEXT: adds r0, #4
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; CHECK-V7M-NEXT: .LBB0_6:
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; CHECK-V7M-NEXT: bx lr
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; CHECK-V7M-NEXT: .LBB0_7:
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; CHECK-V7M-NEXT: add r0, r1
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; CHECK-V7M-NEXT: adds r0, #1
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; CHECK-V7M-NEXT: bx lr
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; CHECK-V7M-NEXT: .LBB0_8:
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; CHECK-V7M-NEXT: add r0, r1
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; CHECK-V7M-NEXT: adds r0, #2
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; CHECK-V7M-NEXT: bx lr
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; CHECK-V7M-NEXT: .p2align 2
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; CHECK-V7M-NEXT: .LCPI0_0:
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; CHECK-V7M-NEXT: .long 537923600
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entry:
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switch i32 %a, label %return [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 30, label %sw.bb3
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i32 50, label %sw.bb5
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]
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sw.bb: ; preds = %entry
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%add = add nsw i32 %b, 537923600
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br label %return
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sw.bb1: ; preds = %entry
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%add2 = add nsw i32 %b, 537923601
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br label %return
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sw.bb3: ; preds = %entry
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%add4 = add nsw i32 %b, 537923602
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br label %return
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sw.bb5: ; preds = %entry
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%add6 = add nsw i32 %b, 537923604
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br label %return
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return: ; preds = %entry, %sw.bb5, %sw.bb3, %sw.bb1, %sw.bb
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%retval.0 = phi i32 [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add2, %sw.bb1 ], [ %add, %sw.bb ], [ 537923600, %entry ]
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ret i32 %retval.0
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}
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define i32 @test_addr(i32 %a, i8* nocapture readonly %b) {
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; CHECK-V6M-LABEL: test_addr:
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; CHECK-V6M: mov r2, r0
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; CHECK-V6M-NEXT: movs r0, #19
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; CHECK-V6M-NEXT: lsls r3, r0, #4
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; CHECK-V6M-NEXT: movs r0, #0
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; CHECK-V6M-NEXT: cmp r2, #29
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; CHECK-V6M-NEXT: bgt .LBB1_4
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; CHECK-V6M-NEXT: cmp r2, #0
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; CHECK-V6M-NEXT: beq .LBB1_8
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; CHECK-V6M-NEXT: cmp r2, #1
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; CHECK-V6M-NEXT: bne .LBB1_9
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; CHECK-V6M-NEXT: adds r3, r3, #1
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; CHECK-V6M-NEXT: b .LBB1_8
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; CHECK-V6M-NEXT: .LBB1_4:
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; CHECK-V6M-NEXT: cmp r2, #30
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; CHECK-V6M-NEXT: beq .LBB1_7
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; CHECK-V6M-NEXT: cmp r2, #50
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; CHECK-V6M-NEXT: bne .LBB1_9
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; CHECK-V6M-NEXT: adds r3, r3, #3
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; CHECK-V6M-NEXT: b .LBB1_8
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; CHECK-V6M-NEXT: .LBB1_7:
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; CHECK-V6M-NEXT: adds r3, r3, #2
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; CHECK-V6M-NEXT: .LBB1_8:
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; CHECK-V6M-NEXT: ldrb r0, [r1, r3]
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; CHECK-V6M-NEXT: .LBB1_9:
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; CHECK-V6M-NEXT: bx lr
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;
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; CHECK-V7M-LABEL: test_addr:
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; CHECK-V7M: mov r2, r0
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; CHECK-V7M-NEXT: movs r0, #0
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; CHECK-V7M-NEXT: cmp r2, #29
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; CHECK-V7M-NEXT: bgt .LBB1_4
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; CHECK-V7M-NEXT: cbz r2, .LBB1_7
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; CHECK-V7M-NEXT: cmp r2, #1
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; CHECK-V7M-NEXT: it ne
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; CHECK-V7M-NEXT: bxne lr
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; CHECK-V7M-NEXT: .LBB1_3:
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; CHECK-V7M-NEXT: movw r0, #305
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; CHECK-V7M-NEXT: b .LBB1_9
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; CHECK-V7M-NEXT: .LBB1_4:
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; CHECK-V7M-NEXT: cmp r2, #30
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; CHECK-V7M-NEXT: beq .LBB1_8
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; CHECK-V7M-NEXT: cmp r2, #50
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; CHECK-V7M-NEXT: bne .LBB1_10
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; CHECK-V7M-NEXT: movw r0, #307
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; CHECK-V7M-NEXT: b .LBB1_9
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; CHECK-V7M-NEXT: .LBB1_7:
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; CHECK-V7M-NEXT: mov.w r0, #304
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; CHECK-V7M-NEXT: b .LBB1_9
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; CHECK-V7M-NEXT: .LBB1_8:
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; CHECK-V7M-NEXT: mov.w r0, #306
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; CHECK-V7M-NEXT: .LBB1_9:
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; CHECK-V7M-NEXT: ldrb r0, [r1, r0]
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; CHECK-V7M-NEXT: .LBB1_10:
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; CHECK-V7M-NEXT: bx lr
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entry:
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switch i32 %a, label %return [
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i32 0, label %return.sink.split
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i32 1, label %sw.bb1
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i32 30, label %sw.bb4
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i32 50, label %sw.bb7
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]
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sw.bb1: ; preds = %entry
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br label %return.sink.split
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sw.bb4: ; preds = %entry
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br label %return.sink.split
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sw.bb7: ; preds = %entry
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br label %return.sink.split
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return.sink.split: ; preds = %entry, %sw.bb1, %sw.bb4, %sw.bb7
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%.sink = phi i32 [ 307, %sw.bb7 ], [ 306, %sw.bb4 ], [ 305, %sw.bb1 ], [ 304, %entry ]
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%arrayidx8 = getelementptr inbounds i8, i8* %b, i32 %.sink
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%0 = load i8, i8* %arrayidx8, align 1
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%phitmp = zext i8 %0 to i32
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br label %return
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return: ; preds = %return.sink.split, %entry
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%retval.0.shrunk = phi i32 [ 0, %entry ], [ %phitmp, %return.sink.split ]
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ret i32 %retval.0.shrunk
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}
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