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https://github.com/RPCS3/llvm-mirror.git
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c04187c6e9
Summary: This patch adds intrinsics for the following MVE instructions: * VABAV * VMLADAV, VMLSDAV * VMLALDAV, VMLSLDAV * VRMLALDAVH, VRMLSLDAVH Each of the above 4 groups has a corresponding new LLVM IR intrinsic, since the instructions cannot be easily represented using general-purpose IR operations. Reviewers: simon_tatham, ostannard, dmgreen, MarkMurrayARM Reviewed By: MarkMurrayARM Subscribers: merge_guards_bot, kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D71062
159 lines
5.6 KiB
LLVM
159 lines
5.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
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declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
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declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
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declare i32 @llvm.arm.mve.vabav.v16i8(i32, i32, <16 x i8>, <16 x i8>)
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declare i32 @llvm.arm.mve.vabav.v8i16(i32, i32, <8 x i16>, <8 x i16>)
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declare i32 @llvm.arm.mve.vabav.v4i32(i32, i32, <4 x i32>, <4 x i32>)
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declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>)
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declare i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32, i32, <8 x i16>, <8 x i16>, <8 x i1>)
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declare i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32, i32, <4 x i32>, <4 x i32>, <4 x i1>)
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define arm_aapcs_vfpcc i32 @test_vabavq_s8(i32 %a, <16 x i8> %b, <16 x i8> %c) {
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; CHECK-LABEL: test_vabavq_s8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vabav.s8 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.arm.mve.vabav.v16i8(i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c)
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ret i32 %0
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_s16(i32 %a, <8 x i16> %b, <8 x i16> %c) {
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; CHECK-LABEL: test_vabavq_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vabav.s16 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.arm.mve.vabav.v8i16(i32 0, i32 %a, <8 x i16> %b, <8 x i16> %c)
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ret i32 %0
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_s32(i32 %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: test_vabavq_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vabav.s32 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.arm.mve.vabav.v4i32(i32 0, i32 %a, <4 x i32> %b, <4 x i32> %c)
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ret i32 %0
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_u8(i32 %a, <16 x i8> %b, <16 x i8> %c) {
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; CHECK-LABEL: test_vabavq_u8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vabav.u8 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.arm.mve.vabav.v16i8(i32 1, i32 %a, <16 x i8> %b, <16 x i8> %c)
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ret i32 %0
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_u16(i32 %a, <8 x i16> %b, <8 x i16> %c) {
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; CHECK-LABEL: test_vabavq_u16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vabav.u16 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.arm.mve.vabav.v8i16(i32 1, i32 %a, <8 x i16> %b, <8 x i16> %c)
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ret i32 %0
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_u32(i32 %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: test_vabavq_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vabav.u32 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = call i32 @llvm.arm.mve.vabav.v4i32(i32 1, i32 %a, <4 x i32> %b, <4 x i32> %c)
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ret i32 %0
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_p_s8(i32 %a, <16 x i8> %b, <16 x i8> %c, i16 zeroext %p) {
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; CHECK-LABEL: test_vabavq_p_s8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vabavt.s8 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
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%2 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %1)
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ret i32 %2
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_p_s16(i32 %a, <8 x i16> %b, <8 x i16> %c, i16 zeroext %p) {
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; CHECK-LABEL: test_vabavq_p_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vabavt.s16 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 0, i32 %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %1)
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ret i32 %2
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_p_s32(i32 %a, <4 x i32> %b, <4 x i32> %c, i16 zeroext %p) {
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; CHECK-LABEL: test_vabavq_p_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vabavt.s32 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 0, i32 %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %1)
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ret i32 %2
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_p_u8(i32 %a, <16 x i8> %b, <16 x i8> %c, i16 zeroext %p) {
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; CHECK-LABEL: test_vabavq_p_u8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vabavt.u8 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
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%2 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %a, <16 x i8> %b, <16 x i8> %c, <16 x i1> %1)
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ret i32 %2
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_p_u16(i32 %a, <8 x i16> %b, <8 x i16> %c, i16 zeroext %p) {
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; CHECK-LABEL: test_vabavq_p_u16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vabavt.u16 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = call i32 @llvm.arm.mve.vabav.predicated.v8i16.v8i1(i32 1, i32 %a, <8 x i16> %b, <8 x i16> %c, <8 x i1> %1)
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ret i32 %2
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}
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define arm_aapcs_vfpcc i32 @test_vabavq_p_u32(i32 %a, <4 x i32> %b, <4 x i32> %c, i16 zeroext %p) {
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; CHECK-LABEL: test_vabavq_p_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vabavt.u32 r0, q0, q1
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call i32 @llvm.arm.mve.vabav.predicated.v4i32.v4i1(i32 1, i32 %a, <4 x i32> %b, <4 x i32> %c, <4 x i1> %1)
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ret i32 %2
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}
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