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a5cb7f1640
Summary:
vclzq maps nicely to the existing target-independent @llvm.ctlz IR
intrinsic. But vclsq ('count leading sign bits') has no corresponding
target-independent intrinsic, so I've made up @llvm.arm.mve.vcls.
This commit adds the unpredicated forms only.
Reviewers: dmgreen, miyuki, MarkMurrayARM, ostannard
Reviewed By: miyuki
Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits
Tags: #clang, #llvm
Differential Revision: https://reviews.llvm.org/D74335
37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
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define arm_aapcs_vfpcc <16 x i8> @test_vclsq_s8(<16 x i8> %a) {
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; CHECK-LABEL: test_vclsq_s8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcls.s8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8> %a)
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ret <16 x i8> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @test_vclsq_s16(<8 x i16> %a) {
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; CHECK-LABEL: test_vclsq_s16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcls.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16> %a)
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @test_vclsq_s32(<4 x i32> %a) {
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; CHECK-LABEL: test_vclsq_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcls.s32 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32> %a)
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ret <4 x i32> %0
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}
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declare <16 x i8> @llvm.arm.mve.vcls.v16i8(<16 x i8>)
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declare <8 x i16> @llvm.arm.mve.vcls.v8i16(<8 x i16>)
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declare <4 x i32> @llvm.arm.mve.vcls.v4i32(<4 x i32>)
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