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https://github.com/RPCS3/llvm-mirror.git
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f40cf5ffb9
This adds code to lower f16 to f32 fp_exts's using an MVE VCVT instructions, similar to a recent similar patch for fp_trunc. Again it goes through the lowering of a BUILD_VECTOR, but is slightly simpler only having to deal with interleaved indices. It adds a VCVTL node to lower to, similar to VCVTN. Differential Revision: https://reviews.llvm.org/D81339
241 lines
8.9 KiB
LLVM
241 lines
8.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
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; i16 -> i32
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define arm_aapcs_vfpcc <4 x i32> @sext_i32_0246(<8 x i16> %src) {
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; CHECK-LABEL: sext_i32_0246:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%out = sext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @sext_i32_1357(<8 x i16> %src) {
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; CHECK-LABEL: sext_i32_1357:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlt.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%out = sext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <8 x i32> @sext_i32_02468101214(<16 x i16> %src) {
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; CHECK-LABEL: sext_i32_02468101214:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s16 q0, q0
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; CHECK-NEXT: vmovlb.s16 q1, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%out = sext <8 x i16> %strided.vec to <8 x i32>
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ret <8 x i32> %out
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}
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define arm_aapcs_vfpcc <8 x i32> @sext_i32_13579111315(<16 x i16> %src) {
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; CHECK-LABEL: sext_i32_13579111315:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlt.s16 q0, q0
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; CHECK-NEXT: vmovlt.s16 q1, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%out = sext <8 x i16> %strided.vec to <8 x i32>
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ret <8 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_i32_0246(<8 x i16> %src) {
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; CHECK-LABEL: zext_i32_0246:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%out = zext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <4 x i32> @zext_i32_1357(<8 x i16> %src) {
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; CHECK-LABEL: zext_i32_1357:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlt.u16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x i16> %src, <8 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%out = zext <4 x i16> %strided.vec to <4 x i32>
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ret <4 x i32> %out
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}
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define arm_aapcs_vfpcc <8 x i32> @zext_i32_02468101214(<16 x i16> %src) {
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; CHECK-LABEL: zext_i32_02468101214:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u16 q0, q0
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; CHECK-NEXT: vmovlb.u16 q1, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%out = zext <8 x i16> %strided.vec to <8 x i32>
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ret <8 x i32> %out
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}
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define arm_aapcs_vfpcc <8 x i32> @zext_i32_13579111315(<16 x i16> %src) {
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; CHECK-LABEL: zext_i32_13579111315:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlt.u16 q0, q0
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; CHECK-NEXT: vmovlt.u16 q1, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i16> %src, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%out = zext <8 x i16> %strided.vec to <8 x i32>
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ret <8 x i32> %out
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}
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; i8 -> i16
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define arm_aapcs_vfpcc <8 x i16> @sext_i16_02468101214(<16 x i8> %src) {
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; CHECK-LABEL: sext_i16_02468101214:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%out = sext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @sext_i16_13579111315(<16 x i8> %src) {
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; CHECK-LABEL: sext_i16_13579111315:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlt.s8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%out = sext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <16 x i16> @sext_i16_024681012141618202224262830(<32 x i8> %src) {
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; CHECK-LABEL: sext_i16_024681012141618202224262830:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.s8 q0, q0
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; CHECK-NEXT: vmovlb.s8 q1, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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%out = sext <16 x i8> %strided.vec to <16 x i16>
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ret <16 x i16> %out
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}
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define arm_aapcs_vfpcc <16 x i16> @sext_i16_135791113151719212325272931(<32 x i8> %src) {
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; CHECK-LABEL: sext_i16_135791113151719212325272931:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlt.s8 q0, q0
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; CHECK-NEXT: vmovlt.s8 q1, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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%out = sext <16 x i8> %strided.vec to <16 x i16>
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ret <16 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @zext_i16_02468101214(<16 x i8> %src) {
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; CHECK-LABEL: zext_i16_02468101214:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%out = zext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <8 x i16> @zext_i16_13579111315(<16 x i8> %src) {
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; CHECK-LABEL: zext_i16_13579111315:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlt.u8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x i8> %src, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%out = zext <8 x i8> %strided.vec to <8 x i16>
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ret <8 x i16> %out
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}
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define arm_aapcs_vfpcc <16 x i16> @zext_i16_024681012141618202224262830(<32 x i8> %src) {
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; CHECK-LABEL: zext_i16_024681012141618202224262830:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlb.u8 q0, q0
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; CHECK-NEXT: vmovlb.u8 q1, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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%out = zext <16 x i8> %strided.vec to <16 x i16>
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ret <16 x i16> %out
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}
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define arm_aapcs_vfpcc <16 x i16> @zext_i16_135791113151719212325272931(<32 x i8> %src) {
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; CHECK-LABEL: zext_i16_135791113151719212325272931:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmovlt.u8 q0, q0
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; CHECK-NEXT: vmovlt.u8 q1, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <32 x i8> %src, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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%out = zext <16 x i8> %strided.vec to <16 x i16>
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ret <16 x i16> %out
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}
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; f16 -> f32
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define arm_aapcs_vfpcc <4 x float> @fpext_0246(<8 x half> %src) {
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; CHECK-LABEL: fpext_0246:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcvtb.f32.f16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x half> %src, <8 x half> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%out = fpext <4 x half> %strided.vec to <4 x float>
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ret <4 x float> %out
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}
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define arm_aapcs_vfpcc <4 x float> @fpext_1357(<8 x half> %src) {
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; CHECK-LABEL: fpext_1357:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcvtt.f32.f16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <8 x half> %src, <8 x half> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%out = fpext <4 x half> %strided.vec to <4 x float>
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ret <4 x float> %out
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}
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define arm_aapcs_vfpcc <8 x float> @fpext_02468101214(<16 x half> %src) {
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; CHECK-LABEL: fpext_02468101214:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcvtb.f32.f16 q0, q0
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; CHECK-NEXT: vcvtb.f32.f16 q1, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%out = fpext <8 x half> %strided.vec to <8 x float>
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ret <8 x float> %out
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}
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define arm_aapcs_vfpcc <8 x float> @fpext_13579111315(<16 x half> %src) {
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; CHECK-LABEL: fpext_13579111315:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vcvtt.f32.f16 q0, q0
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; CHECK-NEXT: vcvtt.f32.f16 q1, q1
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; CHECK-NEXT: bx lr
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entry:
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%strided.vec = shufflevector <16 x half> %src, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%out = fpext <8 x half> %strided.vec to <8 x float>
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ret <8 x float> %out
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}
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