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2221e69a13
Removed the HasT2ExtractPack feature and replaced its references with HasDSP. This then allows the Thumb2 extend instructions to be selected for ARMv8M +dsp. These instruction descriptions have also been refactored and more target tests have been added for their isel. Differential Revision: https://reviews.llvm.org/D29623 llvm-svn: 295452
113 lines
2.5 KiB
LLVM
113 lines
2.5 KiB
LLVM
; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m3 %s -o - | FileCheck %s --check-prefix=CHECK-NO-DSP
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; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m4 %s -o - | FileCheck %s --check-prefix=CHECK-DSP
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; RUN: llc -mtriple=thumbv7em-eabi %s -o - | FileCheck %s -check-prefix=CHECK-DSP
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; RUN: llc -mtriple=thumbv8m.main-none-eabi %s -o - | FileCheck %s -check-prefix=CHECK-NO-DSP
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; RUN: llc -mtriple=thumbv8m.main-none-eabi -mattr=+dsp %s -o - | FileCheck %s -check-prefix=CHECK-DSP
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define i32 @test1(i16 zeroext %z) nounwind {
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; CHECK-LABEL: test1:
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; CHECK-DSP: sxth
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; CHECK-NO-DSP: sxth
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%r = sext i16 %z to i32
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ret i32 %r
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}
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define i32 @test2(i8 zeroext %z) nounwind {
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; CHECK-LABEL: test2:
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; CHECK-DSP: sxtb
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; CHECK-NO-DSP: sxtb
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%r = sext i8 %z to i32
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ret i32 %r
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}
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define i32 @test3(i16 signext %z) nounwind {
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; CHECK-LABEL: test3:
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; CHECK-DSP: uxth
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; CHECK-NO-DSP: uxth
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%r = zext i16 %z to i32
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ret i32 %r
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}
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define i32 @test4(i8 signext %z) nounwind {
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; CHECK-LABEL: test4:
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; CHECK-DSP: uxtb
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; CHECK-NO-DSP: uxtb
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%r = zext i8 %z to i32
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ret i32 %r
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}
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define i32 @test5(i32 %a, i8 %b) {
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; CHECK-LABEL: test5:
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; CHECK-DSP: sxtab r0, r0, r1
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; CHECK-NO-DSP-NOT: sxtab
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%sext = sext i8 %b to i32
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%add = add i32 %a, %sext
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ret i32 %add
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}
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define i32 @test6(i32 %a, i32 %b) {
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; CHECK-LABEL: test6:
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; CHECK-DSP: sxtab r0, r0, r1
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; CHECK-NO-DSP-NOT: sxtab
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%shl = shl i32 %b, 24
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%ashr = ashr i32 %shl, 24
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%add = add i32 %a, %ashr
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ret i32 %add
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}
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define i32 @test7(i32 %a, i16 %b) {
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; CHECK-LABEL: test7:
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; CHECK-DSP: sxtah r0, r0, r1
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; CHECK-NO-DSPNOT: sxtah
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%sext = sext i16 %b to i32
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%add = add i32 %a, %sext
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ret i32 %add
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}
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define i32 @test8(i32 %a, i32 %b) {
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; CHECK-LABEL: test8:
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; CHECK-DSP: sxtah r0, r0, r1
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; CHECK-NO-DSP-NOT: sxtah
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%shl = shl i32 %b, 16
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%ashr = ashr i32 %shl, 16
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%add = add i32 %a, %ashr
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ret i32 %add
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}
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define i32 @test9(i32 %a, i8 %b) {
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; CHECK-LABEL: test9:
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; CHECK-DSP: uxtab r0, r0, r1
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; CHECK-NO-DSP-NOT: uxtab
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%zext = zext i8 %b to i32
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%add = add i32 %a, %zext
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ret i32 %add
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}
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define i32 @test10(i32 %a, i32 %b) {
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;CHECK-LABEL: test10:
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;CHECK-DSP: uxtab r0, r0, r1
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;CHECK-NO-DSP-NOT: uxtab
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%and = and i32 %b, 255
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%add = add i32 %a, %and
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ret i32 %add
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}
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define i32 @test11(i32 %a, i16 %b) {
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; CHECK-LABEL: test11:
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; CHECK-DSP: uxtah r0, r0, r1
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; CHECK-NO-DSP-NOT: uxtah
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%zext = zext i16 %b to i32
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%add = add i32 %a, %zext
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ret i32 %add
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}
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define i32 @test12(i32 %a, i32 %b) {
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;CHECK-LABEL: test12:
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;CHECK-DSP: uxtah r0, r0, r1
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;CHECK-NO-DSP-NOT: uxtah
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%and = and i32 %b, 65535
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%add = add i32 %a, %and
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ret i32 %add
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}
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