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https://github.com/RPCS3/llvm-mirror.git
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7743098c5d
This patch adds initial support for a DemandedElts mask to the internal computeKnownBits/ComputeNumSignBits methods, matching the SelectionDAG and GlobalISel equivalents. So far only a couple of instructions have been setup to handle the DemandedElts, the remainder still using the existing 'all elements' default. The plan is to extend support as we have test coverage. Differential Revision: https://reviews.llvm.org/D73435
123 lines
4.6 KiB
LLVM
123 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; This test makes sure that these instructions are properly eliminated.
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;
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i32 @shl_C1_add_A_C2_i32(i16 %A) {
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; CHECK-LABEL: @shl_C1_add_A_C2_i32(
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; CHECK-NEXT: [[B:%.*]] = zext i16 [[A:%.*]] to i32
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; CHECK-NEXT: [[D:%.*]] = shl i32 192, [[B]]
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; CHECK-NEXT: ret i32 [[D]]
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;
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%B = zext i16 %A to i32
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%C = add i32 %B, 5
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%D = shl i32 6, %C
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ret i32 %D
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}
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define i32 @ashr_C1_add_A_C2_i32(i32 %A) {
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; CHECK-LABEL: @ashr_C1_add_A_C2_i32(
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; CHECK-NEXT: ret i32 0
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;
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%B = and i32 %A, 65535
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%C = add i32 %B, 5
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%D = ashr i32 6, %C
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ret i32 %D
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}
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define i32 @lshr_C1_add_A_C2_i32(i32 %A) {
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; CHECK-LABEL: @lshr_C1_add_A_C2_i32(
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; CHECK-NEXT: [[B:%.*]] = and i32 [[A:%.*]], 65535
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; CHECK-NEXT: [[D:%.*]] = shl i32 192, [[B]]
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; CHECK-NEXT: ret i32 [[D]]
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;
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%B = and i32 %A, 65535
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%C = add i32 %B, 5
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%D = shl i32 6, %C
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ret i32 %D
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}
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define <4 x i32> @shl_C1_add_A_C2_v4i32(<4 x i16> %A) {
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; CHECK-LABEL: @shl_C1_add_A_C2_v4i32(
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; CHECK-NEXT: [[B:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32>
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; CHECK-NEXT: [[D:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 undef, i32 -458752>, [[B]]
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; CHECK-NEXT: ret <4 x i32> [[D]]
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;
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%B = zext <4 x i16> %A to <4 x i32>
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%C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
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%D = shl <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
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ret <4 x i32> %D
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}
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define <4 x i32> @ashr_C1_add_A_C2_v4i32(<4 x i32> %A) {
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; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32(
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; CHECK-NEXT: [[B:%.*]] = and <4 x i32> [[A:%.*]], <i32 0, i32 15, i32 255, i32 65535>
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; CHECK-NEXT: [[D:%.*]] = ashr <4 x i32> <i32 6, i32 1, i32 undef, i32 -1>, [[B]]
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; CHECK-NEXT: ret <4 x i32> [[D]]
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;
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%B = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
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%C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
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%D = ashr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
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ret <4 x i32> %D
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}
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define <4 x i32> @lshr_C1_add_A_C2_v4i32(<4 x i32> %A) {
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; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32(
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; CHECK-NEXT: [[B:%.*]] = and <4 x i32> [[A:%.*]], <i32 0, i32 15, i32 255, i32 65535>
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; CHECK-NEXT: [[D:%.*]] = lshr <4 x i32> <i32 6, i32 1, i32 undef, i32 65535>, [[B]]
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; CHECK-NEXT: ret <4 x i32> [[D]]
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;
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%B = and <4 x i32> %A, <i32 0, i32 15, i32 255, i32 65535>
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%C = add <4 x i32> %B, <i32 0, i32 1, i32 50, i32 16>
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%D = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %C
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ret <4 x i32> %D
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}
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define <4 x i32> @shl_C1_add_A_C2_v4i32_splat(i16 %I) {
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; CHECK-LABEL: @shl_C1_add_A_C2_v4i32_splat(
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; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i32 0
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; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[E:%.*]] = shl <4 x i32> <i32 6, i32 4, i32 undef, i32 -458752>, [[C]]
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; CHECK-NEXT: ret <4 x i32> [[E]]
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;
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%A = zext i16 %I to i32
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%B = insertelement <4 x i32> undef, i32 %A, i32 0
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%C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
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%D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
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%E = shl <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
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ret <4 x i32> %E
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}
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define <4 x i32> @ashr_C1_add_A_C2_v4i32_splat(i16 %I) {
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; CHECK-LABEL: @ashr_C1_add_A_C2_v4i32_splat(
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; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i32 0
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; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[E:%.*]] = ashr <4 x i32> <i32 6, i32 1, i32 undef, i32 -1>, [[C]]
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; CHECK-NEXT: ret <4 x i32> [[E]]
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;
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%A = zext i16 %I to i32
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%B = insertelement <4 x i32> undef, i32 %A, i32 0
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%C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
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%D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
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%E = ashr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
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ret <4 x i32> %E
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}
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define <4 x i32> @lshr_C1_add_A_C2_v4i32_splat(i16 %I) {
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; CHECK-LABEL: @lshr_C1_add_A_C2_v4i32_splat(
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; CHECK-NEXT: [[A:%.*]] = zext i16 [[I:%.*]] to i32
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; CHECK-NEXT: [[B:%.*]] = insertelement <4 x i32> undef, i32 [[A]], i32 0
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; CHECK-NEXT: [[C:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[E:%.*]] = lshr <4 x i32> <i32 6, i32 1, i32 undef, i32 65535>, [[C]]
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; CHECK-NEXT: ret <4 x i32> [[E]]
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;
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%A = zext i16 %I to i32
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%B = insertelement <4 x i32> undef, i32 %A, i32 0
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%C = shufflevector <4 x i32> %B, <4 x i32> undef, <4 x i32> zeroinitializer
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%D = add <4 x i32> %C, <i32 0, i32 1, i32 50, i32 16>
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%E = lshr <4 x i32> <i32 6, i32 2, i32 1, i32 -7>, %D
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ret <4 x i32> %E
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}
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