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Hsiangkai Wang 00fc860b80 [RISCV] Implement vsseg intrinsics.
Define vsseg intrinsics and pseudo instructions. Lower vsseg intrinsics
to pseudo instructions in RISCVDAGToDAGISel.

Differential Revision: https://reviews.llvm.org/D94688
2021-01-21 11:51:35 +08:00
benchmarks
bindings [Go] Fix bindings/go/llvm/IRBindings.cpp 2020-12-16 10:09:58 -08:00
cmake Reland [lldb][docs] Use sphinx instead of epydoc to generate LLDB's Python reference 2021-01-17 12:13:01 +01:00
docs [NFC][AMDGPU] Document target ID syntax for code object V2 to V3 2021-01-20 21:48:52 +00:00
examples [Orc] Fix OrcV2Examples after D94690 2021-01-15 13:45:46 +01:00
include [RISCV] Implement vsseg intrinsics. 2021-01-21 11:51:35 +08:00
lib [RISCV] Implement vsseg intrinsics. 2021-01-21 11:51:35 +08:00
projects llvmbuildectomy - replace llvm-build by plain cmake 2020-11-13 10:35:24 +01:00
resources
runtimes [CMake] Split the target side of runtimes build 2021-01-11 23:39:36 -08:00
test [RISCV] Implement vsseg intrinsics. 2021-01-21 11:51:35 +08:00
tools [dsymutil] Compare object modification times using second precision 2021-01-20 18:45:30 -08:00
unittests D94954: Fixes Snapdragon Kryo CPU core detection 2021-01-20 22:23:43 +00:00
utils [gn build] Port 95ce32c7878d 2021-01-20 21:18:20 +00:00
.clang-format
.clang-tidy
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CMakeLists.txt [CMake] Remove dead code setting policies to NEW 2021-01-19 17:19:36 +02:00
CODE_OWNERS.TXT Change XCore code owner. 2021-01-14 12:13:48 +00:00
configure
CREDITS.TXT [NFC] Add contributors names to CREDITS.TXT 2020-10-07 13:22:55 -04:00
LICENSE.TXT
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