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acf02ee748
Differential Revision: http://reviews.llvm.org/D17068 This changes contains fix for failing test-suite. So, this patch should hopefully work now. llvm-svn: 266171
27 lines
1.0 KiB
LLVM
27 lines
1.0 KiB
LLVM
; RUN: llc %s -march=mips -mcpu=mips32r3 -mattr=micromips -filetype=asm \
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; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
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; RUN: llc %s -march=mips64 -mcpu=mips64r3 -mattr=micromips -filetype=asm \
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; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
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; The purpose of this test is to check whether the CodeGen selects
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; LW16 instruction with the base register in a range of $2-$7, $16, $17.
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%struct.T = type { i32 }
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$_ZN1TaSERKS_ = comdat any
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define linkonce_odr void @_ZN1TaSERKS_(%struct.T* %this, %struct.T* dereferenceable(4) %t) #0 comdat align 2 {
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entry:
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%this.addr = alloca %struct.T*, align 4
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%t.addr = alloca %struct.T*, align 4
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%this1 = load %struct.T*, %struct.T** %this.addr, align 4
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%0 = load %struct.T*, %struct.T** %t.addr, align 4
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%V3 = getelementptr inbounds %struct.T, %struct.T* %0, i32 0, i32 0
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%1 = load i32, i32* %V3, align 4
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%V4 = getelementptr inbounds %struct.T, %struct.T* %this1, i32 0, i32 0
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store i32 %1, i32* %V4, align 4
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ret void
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}
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; CHECK: lw16 ${{[0-9]+}}, 0(${{[2-7]|16|17}})
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