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012bf3f3ac
My understanding (from reading just the llvm code) is that * most ppc cpus have a "sync n" instruction and an msync alias that is "sync 0". * "book e" cpus instead have a msync instruction and not the more general "sync n" This patch reflects that in the .td files, allowing a single codepath for asm ond obj streamer and incidentelly fixes a crash when EmitRawText was called on a obj streamer. llvm-svn: 199832
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