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b9654f5566
Summary: The code previously always used s1 as it was using the user + system SGPR information for compute kernels. This is incorrect for Mesa shaders though, The register should be the next SGPR after all user and system SGPR's. We use that Mesa adds arguments for all input and system SGPR's and take the next available SGPR for the scratch wave offset register. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewers: mareko, arsenm, nhaehnle, tstellarAMD Subscribers: qcolombet, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D18941 Patch By: Bas Nieuwenhuizen llvm-svn: 266336
47 lines
1.8 KiB
LLVM
47 lines
1.8 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=bonaire < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=ALL %s
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; RUN: llc -march=amdgcn -mcpu=carrizo < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=ALL %s
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; ALL-LABEL: {{^}}large_alloca_pixel_shader:
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; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
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; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
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; GCN: s_mov_b32 s10, -1
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; CI: s_mov_b32 s11, 0x98f000
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; VI: s_mov_b32 s11, 0x980000
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; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s0 offen
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; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s0 offen
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; ALL: ; ScratchSize: 32772
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define amdgpu_ps void @large_alloca_pixel_shader(i32 %x, i32 %y) #0 {
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%large = alloca [8192 x i32], align 4
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%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191
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store volatile i32 %x, i32* %gep
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%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y
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%val = load volatile i32, i32* %gep1
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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; ALL-LABEL: {{^}}large_alloca_pixel_shader_inreg:
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; GCN: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
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; GCN: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
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; GCN: s_mov_b32 s10, -1
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; CI: s_mov_b32 s11, 0x98f000
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; VI: s_mov_b32 s11, 0x980000
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; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s2 offen
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; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s2 offen
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; ALL: ; ScratchSize: 32772
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define amdgpu_ps void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #0 {
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%large = alloca [8192 x i32], align 4
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%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191
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store volatile i32 %x, i32* %gep
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%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y
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%val = load volatile i32, i32* %gep1
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store volatile i32 %val, i32 addrspace(1)* undef
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ret void
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}
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attributes #0 = { nounwind }
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