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d1f5a2789e
This patch improves the memory folding of the inserted float element for the (V)INSERTPS instruction. The existing implementation occurs in the DAGCombiner and relies on the narrowing of a whole vector load into a scalar load (and then converted into a vector) to (hopefully) allow folding to occur later on. Not only has this proven problematic for debug builds, it also prevents other memory folds (notably stack reloads) from happening. This patch removes the old implementation and moves the folding code to the X86 foldMemoryOperand handler. A new private 'special case' function - foldMemoryOperandCustom - has been added to deal with memory folding of instructions that can't just use the lookup tables - (V)INSERTPS is the first of several that could be done. It also tweaks the memory operand folding code with an additional pointer offset that allows existing memory addresses to be modified, in this case to convert the vector address to the explicit address of the scalar element that will be inserted. Unlike the previous implementation we now set the insertion source index to zero, although this is ignored for the (V)INSERTPSrm version, anything that relied on shuffle decodes (such as unfolding of insertps loads) was incorrectly calculating the source address - I've added a test for this at insertps-unfold-load-bug.ll Differential Revision: http://reviews.llvm.org/D13988 llvm-svn: 252074
137 lines
5.7 KiB
LLVM
137 lines
5.7 KiB
LLVM
; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx | FileCheck %s -check-prefix=X32 --check-prefix=CHECK
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx | FileCheck %s -check-prefix=X64 --check-prefix=CHECK
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define <4 x i32> @blendvb_fallback_v4i32(<4 x i1> %mask, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-LABEL: @blendvb_fallback_v4i32
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; CHECK: vblendvps
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; CHECK: ret
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%ret = select <4 x i1> %mask, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %ret
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}
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define <8 x i32> @blendvb_fallback_v8i32(<8 x i1> %mask, <8 x i32> %x, <8 x i32> %y) {
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; CHECK-LABEL: @blendvb_fallback_v8i32
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; CHECK: vblendvps
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; CHECK: ret
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%ret = select <8 x i1> %mask, <8 x i32> %x, <8 x i32> %y
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ret <8 x i32> %ret
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}
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define <8 x float> @blendvb_fallback_v8f32(<8 x i1> %mask, <8 x float> %x, <8 x float> %y) {
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; CHECK-LABEL: @blendvb_fallback_v8f32
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; CHECK: vblendvps
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; CHECK: ret
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%ret = select <8 x i1> %mask, <8 x float> %x, <8 x float> %y
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ret <8 x float> %ret
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}
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
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define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
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; CHECK-LABEL: insertps_from_vector_load:
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; On X32, account for the argument's move to registers
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; X32: movl 4(%esp), %eax
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; CHECK-NOT: mov
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; CHECK: vinsertps $48, (%{{...}}), {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
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; CHECK-NEXT: ret
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%1 = load <4 x float>, <4 x float>* %pb, align 16
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%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 48)
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ret <4 x float> %2
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}
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;; Use a non-zero CountS for insertps
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define <4 x float> @insertps_from_vector_load_offset(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
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; CHECK-LABEL: insertps_from_vector_load_offset:
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; On X32, account for the argument's move to registers
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; X32: movl 4(%esp), %eax
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; CHECK-NOT: mov
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;; Try to match a bit more of the instr, since we need the load's offset.
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; CHECK: vinsertps $32, 4(%{{...}}), {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
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; CHECK-NEXT: ret
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%1 = load <4 x float>, <4 x float>* %pb, align 16
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%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
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ret <4 x float> %2
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}
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define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x float>* nocapture readonly %pb, i64 %index) {
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; CHECK-LABEL: insertps_from_vector_load_offset_2:
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; On X32, account for the argument's move to registers
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; X32: movl 4(%esp), %eax
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; X32: movl 8(%esp), %ecx
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; CHECK-NOT: mov
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;; Try to match a bit more of the instr, since we need the load's offset.
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; CHECK: vinsertps $0, 12(%{{...}},%{{...}}), {{.*#+}} xmm0 = mem[0],xmm0[1,2,3]
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; CHECK-NEXT: ret
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%1 = getelementptr inbounds <4 x float>, <4 x float>* %pb, i64 %index
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%2 = load <4 x float>, <4 x float>* %1, align 16
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%3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
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ret <4 x float> %3
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}
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define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocapture readonly %fb, i64 %index) {
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; CHECK-LABEL: insertps_from_broadcast_loadf32:
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; On X32, account for the arguments' move to registers
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; X32: movl 8(%esp), %eax
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; X32: movl 4(%esp), %ecx
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; CHECK-NOT: mov
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; CHECK: insertps $48
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; CHECK-NEXT: ret
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%1 = getelementptr inbounds float, float* %fb, i64 %index
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%2 = load float, float* %1, align 4
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%3 = insertelement <4 x float> undef, float %2, i32 0
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%4 = insertelement <4 x float> %3, float %2, i32 1
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%5 = insertelement <4 x float> %4, float %2, i32 2
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%6 = insertelement <4 x float> %5, float %2, i32 3
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%7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
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ret <4 x float> %7
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}
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define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float>* nocapture readonly %b) {
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; CHECK-LABEL: insertps_from_broadcast_loadv4f32:
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; On X32, account for the arguments' move to registers
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; X32: movl 4(%esp), %{{...}}
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; CHECK-NOT: mov
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; CHECK: insertps $48
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; CHECK-NEXT: ret
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%1 = load <4 x float>, <4 x float>* %b, align 4
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%2 = extractelement <4 x float> %1, i32 0
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%3 = insertelement <4 x float> undef, float %2, i32 0
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%4 = insertelement <4 x float> %3, float %2, i32 1
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%5 = insertelement <4 x float> %4, float %2, i32 2
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%6 = insertelement <4 x float> %5, float %2, i32 3
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%7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
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ret <4 x float> %7
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}
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;; FIXME: We're emitting an extraneous pshufd/vbroadcast.
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define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* nocapture readonly %fb, i64 %index) {
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; CHECK-LABEL: insertps_from_broadcast_multiple_use:
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; On X32, account for the arguments' move to registers
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; X32: movl 8(%esp), %eax
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; X32: movl 4(%esp), %ecx
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; CHECK: vbroadcastss
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; CHECK-NOT: mov
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; CHECK: insertps $48
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; CHECK: insertps $48
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; CHECK: insertps $48
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; CHECK: insertps $48
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; CHECK: vaddps
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; CHECK: vaddps
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; CHECK: vaddps
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; CHECK-NEXT: ret
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%1 = getelementptr inbounds float, float* %fb, i64 %index
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%2 = load float, float* %1, align 4
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%3 = insertelement <4 x float> undef, float %2, i32 0
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%4 = insertelement <4 x float> %3, float %2, i32 1
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%5 = insertelement <4 x float> %4, float %2, i32 2
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%6 = insertelement <4 x float> %5, float %2, i32 3
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%7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
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%8 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %b, <4 x float> %6, i32 48)
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%9 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %c, <4 x float> %6, i32 48)
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%10 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %d, <4 x float> %6, i32 48)
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%11 = fadd <4 x float> %7, %8
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%12 = fadd <4 x float> %9, %10
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%13 = fadd <4 x float> %11, %12
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ret <4 x float> %13
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}
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