Ulrich Weigand 020e6c5a45 [SystemZ] Support load-and-zero-rightmost-byte facility ... This adds support for the LZRF/LZRG/LLZRGF instructions that were added on z13, and uses them for code generation were appropriate. SystemZDAGToDAGISel::tryRISBGZero is updated again to prefer LLZRGF over RISBG where both would be possible. llvm-svn: 286586		2016-11-11 12:46:28 +00:00
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AArch64	AArch64: TableGenerate system instruction operands.	2016-07-05 21:23:04 +00:00
AMDGPU	[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.	2016-10-31 16:07:39 +00:00
ARM	[ARM] Saturation instructions are DSP-only	2016-07-25 22:25:25 +00:00
Hexagon	[Hexagon] Treat all conditional branches as predicted (not-taken by default)	2016-05-09 18:22:07 +00:00
Lanai	[lanai] Add Lanai backend.	2016-03-28 13:09:54 +00:00
Mips	[mips] Fix aui/daui/dahi/dati for MIPSR6	2016-10-14 09:31:42 +00:00
PowerPC	[PPC] add absolute difference altivec instructions and matching intrinsics	2016-10-31 19:47:52 +00:00
Sparc	This change adds co-processor condition branching and conditional traps to the Sparc back-end.	2016-03-09 18:20:21 +00:00
SystemZ	[SystemZ] Support load-and-zero-rightmost-byte facility	2016-11-11 12:46:28 +00:00
X86	Add new flag and intrinsic support for MWAITX and MONITORX instructions	2016-05-18 11:59:12 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00