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028d2e0885
Specifically, itineraries for LEON processors has been added, along with several LEON processor Subtargets. Although currently all these targets are pretty much identical, support for features that will differ among these processors will be added in the very near future. The different Instruction Itinerary Classes (IICs) added are sufficient to differentiate between the instruction timings used by LEON and, quite probably, by generic Sparc processors too, but the focus of the exercise has been for LEON processors, as the requirement of my project. If the IICs are not sufficient for other Sparc processor types and you want to add a new itinerary for one of those, it should be relatively trivial to adapt this. As none of the LEON processors has Quad Floats, or is a Version 9 processor, none of those instructions have itinerary classes defined and revert to the default "NoItinerary" instruction itinerary. Phabricator Review: http://reviews.llvm.org/D19359 llvm-svn: 267121
97 lines
3.1 KiB
C++
97 lines
3.1 KiB
C++
//===-- SparcSubtarget.h - Define Subtarget for the SPARC -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the SPARC specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPARC_SPARCSUBTARGET_H
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#define LLVM_LIB_TARGET_SPARC_SPARCSUBTARGET_H
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#include "SparcFrameLowering.h"
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#include "SparcISelLowering.h"
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#include "SparcInstrInfo.h"
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#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "SparcGenSubtargetInfo.inc"
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namespace llvm {
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class StringRef;
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class SparcSubtarget : public SparcGenSubtargetInfo {
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virtual void anchor();
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bool IsV9;
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bool IsLeon;
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bool V8DeprecatedInsts;
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bool IsVIS, IsVIS2, IsVIS3;
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bool Is64Bit;
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bool HasHardQuad;
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bool UsePopc;
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SparcInstrInfo InstrInfo;
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SparcTargetLowering TLInfo;
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SelectionDAGTargetInfo TSInfo;
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SparcFrameLowering FrameLowering;
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public:
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SparcSubtarget(const Triple &TT, const std::string &CPU,
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const std::string &FS, TargetMachine &TM, bool is64bit);
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const SparcInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const TargetFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const SparcRegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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const SparcTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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bool enableMachineScheduler() const override;
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bool isV9() const { return IsV9; }
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bool isLeon() const { return IsLeon; }
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bool isVIS() const { return IsVIS; }
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bool isVIS2() const { return IsVIS2; }
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bool isVIS3() const { return IsVIS3; }
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bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
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bool hasHardQuad() const { return HasHardQuad; }
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bool usePopc() const { return UsePopc; }
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/// ParseSubtargetFeatures - Parses features string setting specified
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/// subtarget options. Definition of function is auto generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
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bool is64Bit() const { return Is64Bit; }
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/// The 64-bit ABI uses biased stack and frame pointers, so the stack frame
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/// of the current function is the area from [%sp+BIAS] to [%fp+BIAS].
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int64_t getStackPointerBias() const {
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return is64Bit() ? 2047 : 0;
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}
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/// Given a actual stack size as determined by FrameInfo, this function
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/// returns adjusted framesize which includes space for register window
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/// spills and arguments.
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int getAdjustedFrameSize(int stackSize) const;
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};
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} // end namespace llvm
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#endif
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