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72d3164a16
Summary: SSBS (Speculative Store Bypass Safe) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SSBS, as it was previously only possible to enable by selecting -march=armv8.5-a. Similar patch upstream in GNU binutils: https://sourceware.org/ml/binutils/2018-09/msg00274.html Reviewers: olista01, samparker, aemerson Reviewed By: samparker Subscribers: javed.absar, kristof.beyls, kristina, llvm-commits Differential Revision: https://reviews.llvm.org/D54629 llvm-svn: 348137
54 lines
2.8 KiB
ArmAsm
54 lines
2.8 KiB
ArmAsm
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+specrestrict < %s | FileCheck %s
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// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s | FileCheck %s
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// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-specrestrict < %s 2>&1 | FileCheck %s --check-prefix=NOSPECID
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mrs x9, ID_PFR2_EL1
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// CHECK: mrs x9, {{id_pfr2_el1|ID_PFR2_EL1}} // encoding: [0x89,0x03,0x38,0xd5]
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// NOSPECID: error: expected readable system register
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// NOSPECID-NEXT: mrs x9, ID_PFR2_EL1
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mrs x8, SCXTNUM_EL0
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mrs x7, SCXTNUM_EL1
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mrs x6, SCXTNUM_EL2
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mrs x5, SCXTNUM_EL3
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mrs x4, SCXTNUM_EL12
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// CHECK: mrs x8, {{scxtnum_el0|SCXTNUM_EL0}} // encoding: [0xe8,0xd0,0x3b,0xd5]
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// CHECK: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}} // encoding: [0xe7,0xd0,0x38,0xd5]
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// CHECK: mrs x6, {{scxtnum_el2|SCXTNUM_EL2}} // encoding: [0xe6,0xd0,0x3c,0xd5]
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// CHECK: mrs x5, {{scxtnum_el3|SCXTNUM_EL3}} // encoding: [0xe5,0xd0,0x3e,0xd5]
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// CHECK: mrs x4, {{scxtnum_el12|SCXTNUM_EL12}} // encoding: [0xe4,0xd0,0x3d,0xd5]
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// NOSPECID: error: expected readable system register
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// NOSPECID-NEXT: mrs x8, {{scxtnum_el0|SCXTNUM_EL0}}
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// NOSPECID: error: expected readable system register
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// NOSPECID-NEXT: mrs x7, {{scxtnum_el1|SCXTNUM_EL1}}
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// NOSPECID: error: expected readable system register
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// NOSPECID-NEXT: mrs x6, {{scxtnum_el2|SCXTNUM_EL2}}
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// NOSPECID: error: expected readable system register
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// NOSPECID-NEXT: mrs x5, {{scxtnum_el3|SCXTNUM_EL3}}
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// NOSPECID: error: expected readable system register
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// NOSPECID-NEXT: mrs x4, {{scxtnum_el12|SCXTNUM_EL12}}
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msr SCXTNUM_EL0, x8
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msr SCXTNUM_EL1, x7
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msr SCXTNUM_EL2, x6
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msr SCXTNUM_EL3, x5
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msr SCXTNUM_EL12, x4
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// CHECK: msr {{scxtnum_el0|SCXTNUM_EL0}}, x8 // encoding: [0xe8,0xd0,0x1b,0xd5]
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// CHECK: msr {{scxtnum_el1|SCXTNUM_EL1}}, x7 // encoding: [0xe7,0xd0,0x18,0xd5]
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// CHECK: msr {{scxtnum_el2|SCXTNUM_EL2}}, x6 // encoding: [0xe6,0xd0,0x1c,0xd5]
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// CHECK: msr {{scxtnum_el3|SCXTNUM_EL3}}, x5 // encoding: [0xe5,0xd0,0x1e,0xd5]
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// CHECK: msr {{scxtnum_el12|SCXTNUM_EL12}}, x4 // encoding: [0xe4,0xd0,0x1d,0xd5]
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// NOSPECID: error: expected writable system register
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// NOSPECID-NEXT: {{scxtnum_el0|SCXTNUM_EL0}}
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// NOSPECID: error: expected writable system register
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// NOSPECID-NEXT: {{scxtnum_el1|SCXTNUM_EL1}}
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// NOSPECID: error: expected writable system register
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// NOSPECID-NEXT: {{scxtnum_el2|SCXTNUM_EL2}}
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// NOSPECID: error: expected writable system register
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// NOSPECID-NEXT: {{scxtnum_el3|SCXTNUM_EL3}}
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// NOSPECID: error: expected writable system register
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// NOSPECID-NEXT: {{scxtnum_el12|SCXTNUM_EL12}}
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