Chandler Carruth 92d324b610 [x86] Initial step of teaching the new vector shuffle lowering about ... PALIGNR. This just adds it to the v8i16 and v16i8 lowering steps where it is completely unmatched. It also introduces the logic for detecting rotation shuffle masks even in the presence of single input or blend masks and arbitrarily undef lanes. I've added fairly comprehensive tests for the matching logic in v8i16 because the tests at that size are much easier to write and manage. I've not checked the SSE2 code generated for these tests because the code is *horrible*. It is absolute madness. Testing it will just make the test brittle without giving any interesting improvements in the correctness confidence. llvm-svn: 218013		2014-09-18 04:11:29 +00:00
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AArch64	[FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ.	2014-09-18 02:44:13 +00:00
ARM	Revert "[ARM, Fix] Fix emitLeading/TrailingFence on old ARM processors"	2014-09-17 18:09:13 +00:00
CPP
Generic
Hexagon
Inputs
Mips	Add mips32 r1 to the list of supported targets for Mips fast-isel	2014-09-15 20:30:25 +00:00
MSP430
NVPTX
PowerPC	Fix FastISel bug in boolean returns for PowerPC.	2014-09-17 23:25:06 +00:00
R600	Exclude known and bugzilled failures from UBSan bootstrap	2014-09-17 20:17:52 +00:00
SPARC	Add back tests for empty function in SPARC and PowerPC.	2014-09-15 22:11:07 +00:00
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X86	[x86] Initial step of teaching the new vector shuffle lowering about	2014-09-18 04:11:29 +00:00
XCore