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7d64810efd
The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
76 lines
3.2 KiB
LLVM
76 lines
3.2 KiB
LLVM
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
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; PHI elimination shouldn't break backedge.
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; rdar://8263994
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%struct.list_data_s = type { i16, i16 }
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%struct.list_head = type { %struct.list_head*, %struct.list_data_s* }
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define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind {
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entry:
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; CHECK-LABEL: t1:
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%0 = icmp eq %struct.list_head* %list, null
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br i1 %0, label %bb2, label %bb
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bb:
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; CHECK: LBB0_[[LABEL:[0-9]]]:
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; CHECK: bne LBB0_[[LABEL]]
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; CHECK-NOT: b LBB0_[[LABEL]]
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; CHECK: bx lr
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%list_addr.05 = phi %struct.list_head* [ %2, %bb ], [ %list, %entry ]
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%next.04 = phi %struct.list_head* [ %list_addr.05, %bb ], [ null, %entry ]
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%1 = getelementptr inbounds %struct.list_head, %struct.list_head* %list_addr.05, i32 0, i32 0
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%2 = load %struct.list_head*, %struct.list_head** %1, align 4
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store %struct.list_head* %next.04, %struct.list_head** %1, align 4
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%3 = icmp eq %struct.list_head* %2, null
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br i1 %3, label %bb2, label %bb
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bb2:
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%next.0.lcssa = phi %struct.list_head* [ null, %entry ], [ %list_addr.05, %bb ]
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ret %struct.list_head* %next.0.lcssa
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}
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; Optimize loop entry, eliminate intra loop branches
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; rdar://8117827
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define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly {
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entry:
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; CHECK-LABEL: t2:
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%0 = icmp eq i32 %passes, 0 ; <i1> [#uses=1]
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br i1 %0, label %bb5, label %bb.nph15
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bb1: ; preds = %bb2.preheader, %bb1
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; CHECK: LBB1_[[PREHDR:.]]: @ %bb2.preheader
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; CHECK: blt LBB1_[[BB3:.]]
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%indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %bb2.preheader ] ; <i32> [#uses=2]
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%sum.08 = phi i32 [ %2, %bb1 ], [ %sum.110, %bb2.preheader ] ; <i32> [#uses=1]
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%tmp17 = sub i32 %i.07, %indvar ; <i32> [#uses=1]
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%scevgep = getelementptr i32, i32* %src, i32 %tmp17 ; <i32*> [#uses=1]
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%1 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1]
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%2 = add nsw i32 %1, %sum.08 ; <i32> [#uses=2]
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%indvar.next = add i32 %indvar, 1 ; <i32> [#uses=2]
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%exitcond = icmp eq i32 %indvar.next, %size ; <i1> [#uses=1]
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br i1 %exitcond, label %bb3, label %bb1
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bb3: ; preds = %bb1, %bb2.preheader
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; CHECK: LBB1_[[BB1:.]]: @ %bb1
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; CHECK: bne LBB1_[[BB1]]
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; CHECK: LBB1_[[BB3]]: @ %bb3
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%sum.0.lcssa = phi i32 [ %sum.110, %bb2.preheader ], [ %2, %bb1 ] ; <i32> [#uses=2]
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%3 = add i32 %pass.011, 1 ; <i32> [#uses=2]
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%exitcond18 = icmp eq i32 %3, %passes ; <i1> [#uses=1]
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br i1 %exitcond18, label %bb5, label %bb2.preheader
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bb.nph15: ; preds = %entry
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%i.07 = add i32 %size, -1 ; <i32> [#uses=2]
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%4 = icmp sgt i32 %i.07, -1 ; <i1> [#uses=1]
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br label %bb2.preheader
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bb2.preheader: ; preds = %bb3, %bb.nph15
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%pass.011 = phi i32 [ 0, %bb.nph15 ], [ %3, %bb3 ] ; <i32> [#uses=1]
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%sum.110 = phi i32 [ 0, %bb.nph15 ], [ %sum.0.lcssa, %bb3 ] ; <i32> [#uses=2]
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br i1 %4, label %bb1, label %bb3
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bb5: ; preds = %bb3, %entry
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%sum.1.lcssa = phi i32 [ 0, %entry ], [ %sum.0.lcssa, %bb3 ] ; <i32> [#uses=1]
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ret i32 %sum.1.lcssa
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}
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