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0192a1dd5e
`saa` and `saad` are 32-bit and 64-bit store atomic add instructions. memory[base] = memory[base] + rt These instructions are available for "Octeon+" CPU. The patch adds support for both instructions to MIPS assembler and diassembler and introduces new CPU type - "octeon+". Next patches will implement `.set arch=octeon+` directive and `AFL_EXT_OCTEONP` ISA extension flag support. Differential Revision: https://reviews.llvm.org/D69849
29 lines
1.5 KiB
ArmAsm
29 lines
1.5 KiB
ArmAsm
# RUN: llvm-mc -triple=mips64 -show-encoding -mcpu=octeon+ %s \
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# RUN: | FileCheck -check-prefix=MIPS64 %s
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saad $2, 8($5)
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# MIPS64: daddiu $1, $5, 8 # encoding: [0x64,0xa1,0x00,0x08]
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# MIPS64-NEXT: saad $2, ($1) # encoding: [0x70,0x22,0x00,0x19]
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saad $2, foo
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# MIPS64: lui $1, %highest(foo) # encoding: [0x3c,0x01,A,A]
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# MIPS64-NEXT: # fixup A - offset: 0, value: %highest(foo), kind: fixup_Mips_HIGHEST
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# MIPS64-NEXT: daddiu $1, $1, %higher(foo) # encoding: [0x64,0x21,A,A]
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# MIPS64-NEXT: # fixup A - offset: 0, value: %higher(foo), kind: fixup_Mips_HIGHER
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# MIPS64-NEXT: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38]
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# MIPS64-NEXT: daddiu $1, $1, %hi(foo) # encoding: [0x64,0x21,A,A]
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# MIPS64-NEXT: # fixup A - offset: 0, value: %hi(foo), kind: fixup_Mips_HI16
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# MIPS64-NEXT: dsll $1, $1, 16 # encoding: [0x00,0x01,0x0c,0x38]
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# MIPS64-NEXT: daddiu $1, $1, %lo(foo) # encoding: [0x64,0x21,A,A]
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# MIPS64-NEXT: # fixup A - offset: 0, value: %lo(foo), kind: fixup_Mips_LO16
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# MIPS64-NEXT: saad $2, ($1) # encoding: [0x70,0x22,0x00,0x19]
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.option pic2
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saad $2, foo
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# MIPS64: ld $1, %got_disp(foo)($gp) # encoding: [0xdf,0x81,A,A]
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# MIPS64-NEXT: # fixup A - offset: 0, value: %got_disp(foo), kind: fixup_Mips_GOT_DISP
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# MIPS64-NEXT: saad $2, ($1) # encoding: [0x70,0x22,0x00,0x19]
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