Matt Arsenault fdf7e5830b AMDGPU: Refactor exp instructions ... Structure the definitions a bit more like the other classes. The main change here is to split EXP with the done bit set to a separate opcode, so we can set mayLoad = 1 so that it won't be reordered before the other exp stores, since this has the special constraint that if the done bit is set then this should be the last exp in she shader. Previously all exp instructions were inferred to have unmodeled side effects. llvm-svn: 288695		2016-12-05 20:23:10 +00:00
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AArch64	[AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber.	2016-11-21 22:51:10 +00:00
AMDGPU	AMDGPU: Refactor exp instructions	2016-12-05 20:23:10 +00:00
ARM	MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it	2016-08-25 01:27:13 +00:00
Generic	[MIRPrinter] XFAIL test for powerpc	2016-11-18 20:08:05 +00:00
Hexagon	[MIRParser] Parse lane masks for register live-ins	2016-10-12 21:06:45 +00:00
Lanai	MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it	2016-08-25 01:27:13 +00:00
Mips	MIRParser: Use shorter cfi identifiers	2016-07-26 18:20:00 +00:00
NVPTX	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
PowerPC	MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.	2016-08-24 01:32:41 +00:00
X86	[MIRPrinter] Print raw branch probabilities as expected by MIRParser	2016-11-18 19:37:24 +00:00