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f1fa2f71c5
Check both operands for use of the $zero register which cannot be used with a compact branch instruction. Reviewers: dsanders, vkalintris Differential Review: https://reviews.llvm.org/D23547 llvm-svn: 278824
131 lines
2.6 KiB
LLVM
131 lines
2.6 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips32r6 -disable-mips-delay-filler < %s | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips32r6 -disable-mips-delay-filler < %s -filetype=obj \
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; RUN: -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
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; RUN: llc -march=mipsel -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s | FileCheck %s
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; RUN: llc -march=mips -mcpu=mips64r6 -disable-mips-delay-filler -target-abi=n64 < %s -filetype=obj \
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; RUN: -o - | llvm-objdump -d - | FileCheck %s -check-prefix=ENCODING
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; bnezc and beqzc have restriction that $rt != 0
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define i32 @f() {
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; CHECK-LABEL: f:
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; CHECK-NOT: bnezc $0
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%cmp = icmp eq i32 1, 1
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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ret i32 1
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if.end:
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ret i32 0
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}
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define i32 @f1() {
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; CHECK-LABEL: f1:
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; CHECK-NOT: beqzc $0
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%cmp = icmp eq i32 0, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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ret i32 1
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if.end:
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ret i32 0
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}
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; We silently fixup cases where the register allocator or user has given us
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; an instruction with incorrect operands that is trivially acceptable.
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; beqc and bnec have the restriction that $rs < $rt.
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define i32 @f2(i32 %a, i32 %b) {
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; ENCODING-LABEL: f2:
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; ENCODING-NOT: beqc $5, $4
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; ENCODING-NOT: bnec $5, $4
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%cmp = icmp eq i32 %b, %a
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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ret i32 1
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if.end:
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ret i32 0
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}
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define i64 @f3() {
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; CHECK-LABEL: f3:
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; CHECK-NOT: bnezc $0
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%cmp = icmp eq i64 1, 1
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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ret i64 1
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if.end:
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ret i64 0
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}
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define i64 @f4() {
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; CHECK-LABEL: f4:
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; CHECK-NOT: beqzc $0
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%cmp = icmp eq i64 0, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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ret i64 1
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if.end:
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ret i64 0
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}
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; We silently fixup cases where the register allocator or user has given us
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; an instruction with incorrect operands that is trivially acceptable.
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; beqc and bnec have the restriction that $rs < $rt.
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define i64 @f5(i64 %a, i64 %b) {
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; ENCODING-LABEL: f5:
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; ENCODING-NOT: beqc $5, $4
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; ENCODING-NOT: bnec $5, $4
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%cmp = icmp eq i64 %b, %a
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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ret i64 1
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if.end:
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ret i64 0
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}
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define i32 @f6(i32 %a) {
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; CHECK-LABEL: f6:
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; CHECK: beqzc ${{[0-9]+}}, $BB
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%cmp = icmp eq i32 %a, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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ret i32 1
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if.end:
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ret i32 0
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}
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define i32 @f7(i32 %a) {
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; CHECK-LABEL: f7:
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; CHECK: bnezc ${{[0-9]+}}, $BB
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%cmp = icmp eq i32 0, %a
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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ret i32 1
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if.end:
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ret i32 0
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}
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