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bc7384fc93
Introduce new versions that follow the IEEE semantics to help with legalization that may need quieted inputs. There are some regressions from inserting unnecessary canonicalizes when these are matched from fast math fcmp + select which should be fixed in a future commit. llvm-svn: 344914
77 lines
2.8 KiB
LLVM
77 lines
2.8 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI-SAFE,GCN,SI %s
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; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=SI-NONAN,GCN,SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI-SAFE,GCN,VI %s
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; RUN: llc -enable-no-nans-fp-math -enable-no-signed-zeros-fp-math -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=VI-NONAN,GCN,VI %s
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; GCN-LABEL: {{^}}min_fneg_select_regression_0:
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; GCN-NOT: v_mul
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; SI-SAFE: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0
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; VI-SAFE: v_cmp_nle_f32_e32 vcc, 1.0, v0
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; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
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; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
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; GCN-NONAN: v_max_f32_e64 v0, -v0, -1.0
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define amdgpu_ps float @min_fneg_select_regression_0(float %a, float %b) #0 {
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%fneg.a = fsub float -0.0, %a
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%cmp.a = fcmp ult float %a, 1.0
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%min.a = select i1 %cmp.a, float %fneg.a, float -1.0
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ret float %min.a
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}
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; GCN-LABEL: {{^}}min_fneg_select_regression_posk_0:
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; GCN-NOT: v_mul
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; SI-SAFE: v_max_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0
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; VI-SAFE: v_cmp_nle_f32_e32 vcc, -1.0, v0
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; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, -1.0, v0, vcc
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; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
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; GCN-NONAN: v_max_f32_e64 v{{[0-9]+}}, -v0, 1.0
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define amdgpu_ps float @min_fneg_select_regression_posk_0(float %a, float %b) #0 {
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%fneg.a = fsub float -0.0, %a
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%cmp.a = fcmp ult float %a, -1.0
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%min.a = select i1 %cmp.a, float %fneg.a, float 1.0
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ret float %min.a
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}
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; GCN-LABEL: {{^}}max_fneg_select_regression_0:
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; GCN-NOT: v_mul
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; SI-SAFE: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], -1.0, -v0
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; VI-SAFE: v_cmp_nge_f32_e32 vcc, 1.0, v0
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; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, 1.0, v0, vcc
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; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
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; GCN-NONAN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, -1.0
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define amdgpu_ps float @max_fneg_select_regression_0(float %a) #0 {
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%fneg.a = fsub float -0.0, %a
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%cmp.a = fcmp ugt float %a, 1.0
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%min.a = select i1 %cmp.a, float %fneg.a, float -1.0
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ret float %min.a
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}
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; GCN-LABEL: {{^}}max_fneg_select_regression_posk_0:
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; GCN-NOT: v_mul
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; SI-SAFE: v_min_legacy_f32_e64 [[MIN:v[0-9]+]], 1.0, -v0
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; VI-SAFE: v_cmp_nge_f32_e32 vcc, -1.0, v0
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; VI-SAFE-NEXT: v_cndmask_b32_e32 v0, -1.0, v0, vcc
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; VI-SAFE-NEXT: v_xor_b32_e32 v0, 0x80000000, v0
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; GCN-NONAN: v_min_f32_e64 [[MIN:v[0-9]+]], -v0, 1.0
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define amdgpu_ps float @max_fneg_select_regression_posk_0(float %a) #0 {
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%fneg.a = fsub float -0.0, %a
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%cmp.a = fcmp ugt float %a, -1.0
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%min.a = select i1 %cmp.a, float %fneg.a, float 1.0
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ret float %min.a
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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