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b9148f5d85
Summary: Extend cachepolicy operand in the new VMEM buffer intrinsics to supply information whether the buffer data is swizzled. Also, propagate this information to MIR. Intrinsics updated: int_amdgcn_raw_buffer_load int_amdgcn_raw_buffer_load_format int_amdgcn_raw_buffer_store int_amdgcn_raw_buffer_store_format int_amdgcn_raw_tbuffer_load int_amdgcn_raw_tbuffer_store int_amdgcn_struct_buffer_load int_amdgcn_struct_buffer_load_format int_amdgcn_struct_buffer_store int_amdgcn_struct_buffer_store_format int_amdgcn_struct_tbuffer_load int_amdgcn_struct_tbuffer_store Furthermore, disable merging of VMEM buffer instructions in SI Load/Store optimizer, if the "swizzled" bit on the instruction is on. The default value of the bit is 0, meaning that data in buffer is linear and buffer instructions can be merged. There is no difference in the generated code with this commit. However, in the future it will be expected that front-ends use buffer intrinsics with correct "swizzled" bit set. Reviewers: arsenm, nhaehnle, tpr Reviewed By: nhaehnle Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, arphaman, jfb, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68200 llvm-svn: 373491
164 lines
5.4 KiB
YAML
164 lines
5.4 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass=simple-register-coalescing,rename-independent-subregs -o - %s | FileCheck -check-prefix=GCN %s
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---
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# GCN-LABEL: name: mac_invalid_operands
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# GCN: undef %18.sub0:vreg_128 = V_MAC_F32_e32 undef %3:vgpr_32, undef %9:vgpr_32, undef %18.sub0, implicit $exec
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name: mac_invalid_operands
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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scratchWaveOffsetReg: '$sgpr4'
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frameOffsetReg: '$sgpr4'
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registers:
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- { id: 0, class: vreg_128 }
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- { id: 1, class: vreg_128 }
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- { id: 2, class: sgpr_64 }
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- { id: 3, class: vgpr_32 }
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- { id: 4, class: vgpr_32 }
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- { id: 5, class: vgpr_32 }
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- { id: 6, class: vgpr_32 }
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- { id: 7, class: sreg_64 }
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- { id: 8, class: vgpr_32 }
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- { id: 9, class: vgpr_32 }
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- { id: 10, class: vreg_64 }
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- { id: 11, class: vreg_64 }
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- { id: 12, class: vreg_128 }
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- { id: 13, class: vreg_128 }
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- { id: 14, class: vgpr_32 }
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- { id: 15, class: vreg_64 }
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- { id: 16, class: vgpr_32 }
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- { id: 17, class: vreg_128 }
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body: |
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bb.0:
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successors: %bb.2, %bb.1
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%7 = V_CMP_NEQ_F32_e64 0, 0, 0, undef %3, 0, implicit $exec
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$vcc = COPY killed %7
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S_CBRANCH_VCCZ %bb.2, implicit killed $vcc
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bb.1:
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successors: %bb.3
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%4 = V_ADD_F32_e32 undef %6, undef %5, implicit $exec
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undef %12.sub0 = COPY killed %4
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%17 = COPY killed %12
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S_BRANCH %bb.3
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bb.2:
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successors: %bb.3
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%8 = V_MAC_F32_e32 undef %3, undef %9, undef %8, implicit $exec
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undef %13.sub0 = COPY %8
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%13.sub1 = COPY %8
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%13.sub2 = COPY killed %8
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%0 = COPY killed %13
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%17 = COPY killed %0
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bb.3:
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%1 = COPY killed %17
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FLAT_STORE_DWORD undef %10, %1.sub2, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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%14 = COPY %1.sub1
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%16 = COPY killed %1.sub0
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undef %15.sub0 = COPY killed %16
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%15.sub1 = COPY killed %14
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FLAT_STORE_DWORDX2 undef %11, killed %15, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
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S_ENDPGM 0
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...
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---
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# Make sure others uses after the mac are properly handled and not
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# left unreplaced due to iterator issues from substituteRegister.
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# GCN-LABEL: name: vreg_does_not_dominate
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# GCN: undef %8.sub1:vreg_128 = V_MAC_F32_e32 undef %2:vgpr_32, undef %1:vgpr_32, undef %8.sub1, implicit $exec
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# GCN: undef %7.sub0:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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# GCN: undef %9.sub2:vreg_128 = COPY %7.sub0
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# GCN: undef %6.sub3:vreg_128 = V_ADD_F32_e32 undef %3:vgpr_32, undef %3:vgpr_32, implicit $exec
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# GCN: undef %7.sub0:vreg_128 = V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit $exec
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# GCN: %8.sub1:vreg_128 = V_ADD_F32_e32 %8.sub1, %8.sub1, implicit $exec
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# GCN: BUFFER_STORE_DWORD_OFFEN %6.sub3, %0,
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# GCN: BUFFER_STORE_DWORD_OFFEN %9.sub2, %0,
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# GCN: BUFFER_STORE_DWORD_OFFEN %8.sub1, %0,
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# GCN: BUFFER_STORE_DWORD_OFFEN %7.sub0, %0,
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name: vreg_does_not_dominate
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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scratchWaveOffsetReg: '$sgpr4'
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frameOffsetReg: '$sgpr4'
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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- { id: 1, class: vgpr_32, preferred-register: '' }
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- { id: 2, class: vgpr_32, preferred-register: '' }
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- { id: 3, class: vgpr_32, preferred-register: '' }
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- { id: 4, class: vgpr_32, preferred-register: '' }
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- { id: 5, class: sreg_64, preferred-register: '' }
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- { id: 6, class: vreg_128, preferred-register: '' }
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liveins:
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- { reg: '$vgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr30_sgpr31', virtual-reg: '%5' }
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body: |
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bb.0:
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successors: %bb.2, %bb.1
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liveins: $vgpr0, $sgpr30_sgpr31, $sgpr5
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%5 = COPY $sgpr30_sgpr31
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%0 = COPY $vgpr0
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undef %6.sub1 = V_MAC_F32_e32 undef %2, undef %1, undef %6.sub1, implicit $exec
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%6.sub0 = V_MOV_B32_e32 0, implicit $exec
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%6.sub2 = COPY %6.sub0
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S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.2
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%6.sub3 = V_ADD_F32_e32 undef %3, undef %3, implicit $exec
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%6.sub0 = V_ADD_F32_e64 0, 0, 0, 0, 0, 0, implicit $exec
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%6.sub1 = V_ADD_F32_e32 %6.sub1, %6.sub1, implicit $exec
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%6.sub2 = COPY %6.sub0
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bb.2:
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BUFFER_STORE_DWORD_OFFEN %6.sub3, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 12, 0, 0, 0, 0, 0, implicit $exec
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BUFFER_STORE_DWORD_OFFEN %6.sub2, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 8, 0, 0, 0, 0, 0, implicit $exec
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BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, 0, 0, implicit $exec
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BUFFER_STORE_DWORD_OFFEN %6.sub0, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, 0, 0, implicit $exec
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$sgpr30_sgpr31 = COPY %5
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S_SETPC_B64_return $sgpr30_sgpr31
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...
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# GCN-LABEL: name: inf_loop_tied_operand
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# GCN: bb.0:
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# GCN-NEXT: undef %2.sub0:vreg_128 = V_MAC_F32_e32 1073741824, undef %0:vgpr_32, undef %2.sub0, implicit $exec
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# GCN-NEXT: dead undef %3.sub1:vreg_128 = COPY %2.sub0
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name: inf_loop_tied_operand
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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- { id: 1, class: vgpr_32, preferred-register: '' }
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- { id: 2, class: vreg_128, preferred-register: '' }
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body: |
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bb.0:
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%1 = V_MAC_F32_e32 1073741824, undef %0, undef %1, implicit $exec
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undef %2.sub0 = COPY %1
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%2.sub1 = COPY %1
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...
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