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0120bda5a7
This adds assembler support for the instructions provided by the execution-hint facility (NIAI and BP(R)P). This required adding support for the new relocation types for 12-bit and 24-bit PC- relative offsets used by the BP(R)P instructions. llvm-svn: 288031
35 lines
1.9 KiB
ArmAsm
35 lines
1.9 KiB
ArmAsm
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# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=zEC12 --show-encoding %s | FileCheck %s
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# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=zEC12 -filetype=obj %s | \
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# RUN: llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
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# CHECK: bpp 12, branch, 0 # encoding: [0xc7,0xc0,0x00,0x00,A,A]
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# CHECK: # fixup A - offset: 4, value: branch+4, kind: FK_390_PC16DBL
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# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_PC16DBL branch 0x4
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.align 16
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bpp 12, branch, 0
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# CHECK: bpp 12, branch@PLT, 0 # encoding: [0xc7,0xc0,0x00,0x00,A,A]
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# CHECK: # fixup A - offset: 4, value: branch@PLT+4, kind: FK_390_PC16DBL
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# CHECK-REL: 0x{{[0-9A-F]*4}} R_390_PLT16DBL branch 0x4
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.align 16
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bpp 12, branch@plt, 0
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# CHECK: bprp 12, branch, target # encoding: [0xc5,0b1100AAAA,A,B,B,B]
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# CHECK-NEXT: # fixup A - offset: 1, value: branch+1, kind: FK_390_PC12DBL
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# CHECK-NEXT: # fixup B - offset: 3, value: target+3, kind: FK_390_PC24DBL
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# CHECK-REL: 0x{{[0-9A-F]*1}} R_390_PC12DBL branch 0x1
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# CHECK-REL: 0x{{[0-9A-F]*3}} R_390_PC24DBL target 0x3
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.align 16
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bprp 12, branch, target
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# CHECK: bprp 12, branch@PLT, target@PLT # encoding: [0xc5,0b1100AAAA,A,B,B,B]
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# CHECK-NEXT: # fixup A - offset: 1, value: branch@PLT+1, kind: FK_390_PC12DBL
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# CHECK-NEXT: # fixup B - offset: 3, value: target@PLT+3, kind: FK_390_PC24DBL
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# CHECK-REL: 0x{{[0-9A-F]*1}} R_390_PLT12DBL branch 0x1
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# CHECK-REL: 0x{{[0-9A-F]*3}} R_390_PLT24DBL target 0x3
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.align 16
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bprp 12, branch@plt, target@plt
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