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https://github.com/RPCS3/llvm-mirror.git
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f4315577b8
This patch generalizes the lowering of shuffles as zero extensions to allow extensions that don't start from the first element. It now recognises extensions starting anywhere in the lower 128-bits or at the start of any higher 128-bit lane. The motivation was to reduce the number of high cost pshufb calls, but it also improves the SSE2 case as well. Differential Revision: http://reviews.llvm.org/D12561 llvm-svn: 248250
110 lines
3.8 KiB
LLVM
110 lines
3.8 KiB
LLVM
; RUN: llc -mtriple=x86_64-apple-macosx -mcpu=nocona -verify-machineinstrs < %s | FileCheck %s
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; After tail duplication, two copies in an early exit BB can be cancelled out.
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; rdar://10640363
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define i32 @t1(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: je [[LABEL:.*BB.*]]
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%cmp1 = icmp eq i32 %b, 0
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br i1 %cmp1, label %while.end, label %while.body
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; CHECK: [[LABEL]]:
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; CHECK-NOT: mov
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; CHECK: ret
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while.body: ; preds = %entry, %while.body
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%a.addr.03 = phi i32 [ %b.addr.02, %while.body ], [ %a, %entry ]
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%b.addr.02 = phi i32 [ %rem, %while.body ], [ %b, %entry ]
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%rem = srem i32 %a.addr.03, %b.addr.02
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%cmp = icmp eq i32 %rem, 0
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br i1 %cmp, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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%a.addr.0.lcssa = phi i32 [ %a, %entry ], [ %b.addr.02, %while.body ]
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ret i32 %a.addr.0.lcssa
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}
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; Two movdqa (from phi-elimination) in the entry BB cancels out.
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; rdar://10428165
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define <8 x i16> @t2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
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entry:
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; CHECK-LABEL: t2:
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; CHECK-NOT: movdqa
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%tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
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ret <8 x i16> %tmp8
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}
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define i32 @t3(i64 %a, i64 %b) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK: je [[LABEL:.*BB.*]]
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%cmp1 = icmp eq i64 %b, 0
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br i1 %cmp1, label %while.end, label %while.body
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; CHECK: [[LABEL]]:
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; CHECK-NOT: mov
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; CHECK: ret
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while.body: ; preds = %entry, %while.body
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%a.addr.03 = phi i64 [ %b.addr.02, %while.body ], [ %a, %entry ]
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%b.addr.02 = phi i64 [ %rem, %while.body ], [ %b, %entry ]
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%rem = srem i64 %a.addr.03, %b.addr.02
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%cmp = icmp eq i64 %rem, 0
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br i1 %cmp, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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%a.addr.0.lcssa = phi i64 [ %a, %entry ], [ %b.addr.02, %while.body ]
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%t = trunc i64 %a.addr.0.lcssa to i32
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ret i32 %t
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}
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; Check that copy propagation does not kill thing like:
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; dst = copy src <-- do not kill that.
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; ... = op1 dst<undef>
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; ... = op2 dst <-- this is used here.
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;
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; CHECK-LABEL: foo:
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; CHECK: psllw $7,
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; CHECK: psllw $7, [[SRC1:%xmm[0-9]+]]
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; CHECK-NEXT: pand {{.*}}(%rip), [[SRC1]]
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; CHECK-NEXT: pcmpgtb [[SRC1]], [[SRC2:%xmm[0-9]+]]
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; CHECK-NEXT: pand %xmm{{[0-9]+}}, [[SRC2]]
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; CHECK-NEXT: movdqa [[SRC2]], [[CPY1:%xmm[0-9]+]]
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; CHECK-NEXT: punpcklbw %xmm{{[0-9]+}}, [[CPY1]]
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; Check that CPY1 is not redefined.
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; CHECK-NOT: , [[CPY1]]
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; CHECK: punpckhwd %xmm{{[0-9]+}}, [[CPY1]]
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; CHECK-NEXT: pslld $31, [[CPY1]]
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; CHECK-NEXT: psrad $31, [[CPY1]]
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; CHECK: punpckhbw %xmm{{[0-9]+}}, [[CPY2:%xmm[0-9]+]]
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; Check that CPY2 is not redefined.
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; CHECK-NOT: , [[CPY2]]
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; CHECK: punpckhwd %xmm{{[0-9]+}}, [[CPY2]]
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; CHECK-NEXT: pslld $31, [[CPY2]]
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; CHECK-NEXT: psrad $31, [[CPY2]]
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define <16 x float> @foo(<16 x float> %x) {
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bb:
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%v3 = icmp slt <16 x i32> undef, zeroinitializer
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%v14 = zext <16 x i1> %v3 to <16 x i32>
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%v16 = fcmp olt <16 x float> %x, zeroinitializer
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%v17 = sext <16 x i1> %v16 to <16 x i32>
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%v18 = zext <16 x i1> %v16 to <16 x i32>
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%v19 = xor <16 x i32> %v14, %v18
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%v20 = or <16 x i32> %v17, undef
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%v21 = fptosi <16 x float> %x to <16 x i32>
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%v22 = sitofp <16 x i32> %v21 to <16 x float>
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%v69 = fcmp ogt <16 x float> %v22, zeroinitializer
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%v75 = and <16 x i1> %v69, %v3
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%v77 = bitcast <16 x float> %v22 to <16 x i32>
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%v79 = sext <16 x i1> %v75 to <16 x i32>
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%v80 = and <16 x i32> undef, %v79
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%v81 = xor <16 x i32> %v77, %v80
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%v82 = and <16 x i32> undef, %v81
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%v83 = xor <16 x i32> %v19, %v82
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%v84 = and <16 x i32> %v83, %v20
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%v85 = xor <16 x i32> %v19, %v84
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%v86 = bitcast <16 x i32> %v85 to <16 x float>
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ret <16 x float> %v86
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}
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