1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 19:12:56 +02:00
llvm-mirror/test/TableGen/condsbit.td
Javed Absar 173ca6da08 [TblGen] Extend !if semantics through new feature !cond
This patch extends TableGen language with !cond operator.
Instead of embedding !if inside !if which can get cumbersome,
one can now use !cond.
Below is an example to convert an integer 'x' into a string:

    !cond(!lt(x,0) : "Negative",
          !eq(x,0) : "Zero",
          !eq(x,1) : "One,
          1        : "MoreThanOne")

Reviewed By: hfinkel, simon_tatham, greened
Differential Revision: https://reviews.llvm.org/D55758

llvm-svn: 352185
2019-01-25 10:25:25 +00:00

16 lines
316 B
TableGen

// check that !cond works well with bit conditional values
// RUN: llvm-tblgen %s | FileCheck %s
// XFAIL: vg_leak
// CHECK: a = 6
// CHECK: a = 5
class A<bit b = 1> {
bit true = 1;
int a = !cond(b: 5, true : 6);
bit c = !cond(b: 0, true : 1);
bits<1> d = !cond(b: 0, true : 1);
}
def X : A<0>;
def Y : A;