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720b561453
Summary: Previously these only worked via NVPTX-specific intrinsics. This change will allow us to convert these target-specific intrinsics into the general LLVM versions, allowing existing LLVM passes to reason about their behavior. It also gets us some minor codegen improvements as-is, from situations where we canonicalize code into one of these llvm intrinsics. Reviewers: majnemer Subscribers: llvm-commits, jholewinski, tra Differential Revision: https://reviews.llvm.org/D24300 llvm-svn: 281092
63 lines
2.4 KiB
LLVM
63 lines
2.4 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
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target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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%class.float3 = type { float, float, float }
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; Function Attrs: nounwind
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; CHECK-LABEL: some_kernel
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define void @some_kernel(%class.float3* nocapture %dst) #0 {
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_ZL11compute_vecRK6float3jb.exit:
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%ret_vec.sroa.8.i = alloca float, align 4
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%0 = tail call i32 @llvm.nvvm.read.ptx.sreg.ctaid.x()
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%1 = tail call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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%2 = mul nsw i32 %1, %0
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%3 = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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%4 = add nsw i32 %2, %3
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%5 = zext i32 %4 to i64
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%6 = bitcast float* %ret_vec.sroa.8.i to i8*
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call void @llvm.lifetime.start(i64 4, i8* %6)
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%7 = and i32 %4, 15
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%8 = icmp eq i32 %7, 0
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%9 = select i1 %8, float 0.000000e+00, float -1.000000e+00
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store float %9, float* %ret_vec.sroa.8.i, align 4
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; CHECK: max.f32 %f{{[0-9]+}}, %f{{[0-9]+}}, 0f00000000
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%10 = fcmp olt float %9, 0.000000e+00
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%ret_vec.sroa.8.i.val = load float, float* %ret_vec.sroa.8.i, align 4
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%11 = select i1 %10, float 0.000000e+00, float %ret_vec.sroa.8.i.val
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call void @llvm.lifetime.end(i64 4, i8* %6)
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%12 = getelementptr inbounds %class.float3, %class.float3* %dst, i64 %5, i32 0
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store float 0.000000e+00, float* %12, align 4
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%13 = getelementptr inbounds %class.float3, %class.float3* %dst, i64 %5, i32 1
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store float %11, float* %13, align 4
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%14 = getelementptr inbounds %class.float3, %class.float3* %dst, i64 %5, i32 2
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store float 0.000000e+00, float* %14, align 4
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.nvvm.read.ptx.sreg.ctaid.x() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.nvvm.read.ptx.sreg.ntid.x() #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() #1
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; Function Attrs: nounwind
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declare void @llvm.lifetime.start(i64, i8* nocapture) #2
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; Function Attrs: nounwind
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declare void @llvm.lifetime.end(i64, i8* nocapture) #2
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "unsafe-fp-math"="true" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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!nvvm.annotations = !{!0}
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!llvm.ident = !{!1}
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!0 = !{void (%class.float3*)* @some_kernel, !"kernel", i32 1}
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!1 = !{!"clang version 3.5.1 (tags/RELEASE_351/final)"}
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