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This abstraction allows us to support the various records that can be placed in the .MIPS.options section in the future. We currently use it to record register usage information (the ODK_REGINFO record in our ELF64 spec). Each .MIPS.options record should subclass MipsOptionRecord and provide an implementation of EmitMipsOptionRecord. Patch by Matheus Almeida and Toma Tabacu llvm-svn: 213522
81 lines
2.7 KiB
C++
81 lines
2.7 KiB
C++
//===-- MipsOptionRecord.h - Abstraction for storing information ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// MipsOptionRecord - Abstraction for storing arbitrary information in
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// ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
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// specific ELF sections like .Mips.options. Specific records should subclass
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// MipsOptionRecord and provide an implementation to EmitMipsOptionRecord which
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// basically just dumps the information into an ELF section. More information
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// about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
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// specification.
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//
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//===----------------------------------------------------------------------===//
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#ifndef MIPSOPTIONRECORD_H
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#define MIPSOPTIONRECORD_H
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#include "MipsMCTargetDesc.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCRegisterInfo.h"
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using namespace llvm;
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namespace llvm {
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class MipsELFStreamer;
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class MCSubtargetInfo;
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}
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class MipsOptionRecord {
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public:
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virtual ~MipsOptionRecord(){};
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virtual void EmitMipsOptionRecord() = 0;
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};
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class MipsRegInfoRecord : public MipsOptionRecord {
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public:
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MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context,
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const MCSubtargetInfo &STI)
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: Streamer(S), Context(Context), STI(STI) {
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ri_gprmask = 0;
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ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0;
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ri_gp_value = 0;
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const MCRegisterInfo *TRI = Context.getRegisterInfo();
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GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
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GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
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FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
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FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
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AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
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MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
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COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
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COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
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}
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~MipsRegInfoRecord() {}
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void EmitMipsOptionRecord();
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void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo);
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private:
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MipsELFStreamer *Streamer;
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MCContext &Context;
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const MCSubtargetInfo &STI;
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const MCRegisterClass *GPR32RegClass;
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const MCRegisterClass *GPR64RegClass;
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const MCRegisterClass *FGR32RegClass;
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const MCRegisterClass *FGR64RegClass;
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const MCRegisterClass *AFGR64RegClass;
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const MCRegisterClass *MSA128BRegClass;
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const MCRegisterClass *COP2RegClass;
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const MCRegisterClass *COP3RegClass;
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uint32_t ri_gprmask;
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uint32_t ri_cprmask[4];
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int64_t ri_gp_value;
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};
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#endif
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