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ee0d5cd952
This adds support for the new 32-bit vector float instructions of z14. This includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions, including new LLVM intrinsics. - Scheduler description support for the instructions. - Update to the vector cost function calculations. In general, CodeGen support for the new v4f32 instructions closely matches support for the existing v2f64 instructions. llvm-svn: 308195
25 lines
703 B
LLVM
25 lines
703 B
LLVM
; Test vector addition on z14.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
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; Test a v4f32 addition.
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define <4 x float> @f1(<4 x float> %dummy, <4 x float> %val1,
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<4 x float> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vfasb %v24, %v26, %v28
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; CHECK: br %r14
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%ret = fadd <4 x float> %val1, %val2
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ret <4 x float> %ret
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}
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; Test an f32 addition that uses vector registers.
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define float @f2(<4 x float> %val1, <4 x float> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: wfasb %f0, %v24, %v26
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; CHECK: br %r14
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%scalar1 = extractelement <4 x float> %val1, i32 0
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%scalar2 = extractelement <4 x float> %val2, i32 0
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%ret = fadd float %scalar1, %scalar2
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ret float %ret
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}
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