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69950e68ba
There's a special case in EmitLoweredSelect() that produces an improved lowering for cmov(cmov) patterns. However this special lowering is currently broken if the inner cmov has multiple users so this patch stops using it in this case. If you wonder why this wasn't fixed by continuing to use the special lowering and inserting a 2nd PHI for the inner cmov: I believe this would incur additional copies/register pressure so the special lowering does not improve upon the normal one anymore in this case. This fixes http://llvm.org/PR26256 (= rdar://24329747) llvm-svn: 258729
276 lines
7.6 KiB
LLVM
276 lines
7.6 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -mtriple=x86_64-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=CMOV
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; RUN: llc < %s -asm-verbose=false -mtriple=i686-unknown-linux | FileCheck %s --check-prefix=CHECK --check-prefix=NOCMOV
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target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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; Test 2xCMOV patterns exposed after legalization.
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; One way to do that is with (select (fcmp une/oeq)), which gets
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; legalized to setp/setne.
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; CHECK-LABEL: test_select_fcmp_oeq_i32:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: cmovnel %esi, %edi
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; CMOV-NEXT: cmovpl %esi, %edi
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; CMOV-NEXT: movl %edi, %eax
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 16(%esp), %eax
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 12(%esp), %eax
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; NOCMOV-NEXT:[[TBB]]:
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; NOCMOV-NEXT: movl (%eax), %eax
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; NOCMOV-NEXT: retl
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define i32 @test_select_fcmp_oeq_i32(float %a, float %b, i32 %c, i32 %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, i32 %c, i32 %d
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ret i32 %r
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}
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; CHECK-LABEL: test_select_fcmp_oeq_i64:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: cmovneq %rsi, %rdi
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; CMOV-NEXT: cmovpq %rsi, %rdi
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; CMOV-NEXT: movq %rdi, %rax
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 20(%esp), %ecx
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl (%ecx), %eax
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; NOCMOV-NEXT: orl $4, %ecx
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; NOCMOV-NEXT: movl (%ecx), %edx
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; NOCMOV-NEXT: retl
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define i64 @test_select_fcmp_oeq_i64(float %a, float %b, i64 %c, i64 %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, i64 %c, i64 %d
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ret i64 %r
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}
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; CHECK-LABEL: test_select_fcmp_une_i64:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: cmovneq %rdi, %rsi
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; CMOV-NEXT: cmovpq %rdi, %rsi
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; CMOV-NEXT: movq %rsi, %rax
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 12(%esp), %ecx
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 20(%esp), %ecx
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl (%ecx), %eax
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; NOCMOV-NEXT: orl $4, %ecx
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; NOCMOV-NEXT: movl (%ecx), %edx
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; NOCMOV-NEXT: retl
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define i64 @test_select_fcmp_une_i64(float %a, float %b, i64 %c, i64 %d) #0 {
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entry:
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%cmp = fcmp une float %a, %b
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%r = select i1 %cmp, i64 %c, i64 %d
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ret i64 %r
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}
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; CHECK-LABEL: test_select_fcmp_oeq_f64:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; CMOV-NEXT: jp [[TBB]]
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; CMOV-NEXT: movaps %xmm2, %xmm3
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; CMOV-NEXT: [[TBB]]:
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: flds 8(%esp)
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; NOCMOV-NEXT: flds 4(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 20(%esp), %eax
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 12(%esp), %eax
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: fldl (%eax)
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; NOCMOV-NEXT: retl
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define double @test_select_fcmp_oeq_f64(float %a, float %b, double %c, double %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, double %c, double %d
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ret double %r
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}
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; CHECK-LABEL: test_select_fcmp_oeq_v4i32:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; CMOV-NEXT: jp [[TBB]]
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; CMOV-NEXT: movaps %xmm2, %xmm3
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; CMOV-NEXT: [[TBB]]:
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; CMOV-NEXT: movaps %xmm3, %xmm0
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; CMOV-NEXT: retq
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; NOCMOV-NEXT: pushl %edi
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; NOCMOV-NEXT: pushl %esi
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; NOCMOV-NEXT: flds 20(%esp)
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; NOCMOV-NEXT: flds 16(%esp)
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; NOCMOV-NEXT: fucompp
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; NOCMOV-NEXT: fnstsw %ax
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; NOCMOV-NEXT: sahf
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; NOCMOV-NEXT: leal 40(%esp), %eax
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 24(%esp), %eax
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl (%eax), %ecx
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; NOCMOV-NEXT: leal 44(%esp), %edx
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 28(%esp), %edx
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl 12(%esp), %eax
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; NOCMOV-NEXT: movl (%edx), %edx
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; NOCMOV-NEXT: leal 48(%esp), %esi
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 32(%esp), %esi
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl (%esi), %esi
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; NOCMOV-NEXT: leal 52(%esp), %edi
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; NOCMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; NOCMOV-NEXT: jp [[TBB]]
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; NOCMOV-NEXT: leal 36(%esp), %edi
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; NOCMOV-NEXT: [[TBB]]:
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; NOCMOV-NEXT: movl (%edi), %edi
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; NOCMOV-NEXT: movl %edi, 12(%eax)
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; NOCMOV-NEXT: movl %esi, 8(%eax)
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; NOCMOV-NEXT: movl %edx, 4(%eax)
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; NOCMOV-NEXT: movl %ecx, (%eax)
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; NOCMOV-NEXT: popl %esi
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; NOCMOV-NEXT: popl %edi
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; NOCMOV-NEXT: retl $4
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define <4 x i32> @test_select_fcmp_oeq_v4i32(float %a, float %b, <4 x i32> %c, <4 x i32> %d) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%r = select i1 %cmp, <4 x i32> %c, <4 x i32> %d
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ret <4 x i32> %r
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}
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; Also make sure we catch the original code-sequence of interest:
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; CMOV: [[ONE_F32_LCPI:.LCPI.*]]:
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; CMOV-NEXT: .long 1065353216
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; CHECK-LABEL: test_zext_fcmp_une:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: movss [[ONE_F32_LCPI]](%rip), %xmm0
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; CMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; CMOV-NEXT: jp [[TBB]]
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; CMOV-NEXT: xorps %xmm0, %xmm0
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; CMOV-NEXT: [[TBB]]:
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; CMOV-NEXT: retq
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; NOCMOV: jne
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; NOCMOV-NEXT: jp
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define float @test_zext_fcmp_une(float %a, float %b) #0 {
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entry:
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%cmp = fcmp une float %a, %b
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%conv1 = zext i1 %cmp to i32
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%conv2 = sitofp i32 %conv1 to float
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ret float %conv2
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}
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; CMOV: [[ONE_F32_LCPI:.LCPI.*]]:
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; CMOV-NEXT: .long 1065353216
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; CHECK-LABEL: test_zext_fcmp_oeq:
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; CMOV-NEXT: ucomiss %xmm1, %xmm0
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; CMOV-NEXT: xorps %xmm0, %xmm0
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; CMOV-NEXT: jne [[TBB:.LBB[0-9_]+]]
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; CMOV-NEXT: jp [[TBB]]
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; CMOV-NEXT: movss [[ONE_F32_LCPI]](%rip), %xmm0
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; CMOV-NEXT: [[TBB]]:
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; CMOV-NEXT: retq
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; NOCMOV: jne
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; NOCMOV-NEXT: jp
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define float @test_zext_fcmp_oeq(float %a, float %b) #0 {
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entry:
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%cmp = fcmp oeq float %a, %b
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%conv1 = zext i1 %cmp to i32
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%conv2 = sitofp i32 %conv1 to float
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ret float %conv2
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}
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attributes #0 = { nounwind }
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@g8 = global i8 0
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; The following test failed because llvm had a bug where a structure like:
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;
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; %vreg12<def> = CMOV_GR8 %vreg7, %vreg11 ... (lt)
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; %vreg13<def> = CMOV_GR8 %vreg12, %vreg11 ... (gt)
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;
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; was lowered to:
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;
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; The first two cmovs got expanded to:
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; BB#0:
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; JL_1 BB#9
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; BB#7:
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; JG_1 BB#9
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; BB#8:
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; BB#9:
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; vreg12 = phi(vreg7, BB#8, vreg11, BB#0, vreg12, BB#7)
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; vreg13 = COPY vreg12
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; Which was invalid as %vreg12 is not the same value as %vreg13
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; CHECK-LABEL: no_cascade_opt:
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; CMOV-DAG: cmpl %edx, %esi
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; CMOV-DAG: movb $20, %al
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; CMOV-DAG: movb $20, %dl
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; CMOV: jl [[BB0:.LBB[0-9_]+]]
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; CMOV: movb %cl, %dl
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; CMOV: [[BB0]]:
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; CMOV: jg [[BB1:.LBB[0-9_]+]]
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; CMOV: movb %dl, %al
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; CMOV: [[BB1]]:
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; CMOV: testl %edi, %edi
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; CMOV: je [[BB2:.LBB[0-9_]+]]
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; CMOV: movb %dl, %al
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; CMOV: [[BB2]]:
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; CMOV: movb %al, g8(%rip)
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; CMOV: retq
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define void @no_cascade_opt(i32 %v0, i32 %v1, i32 %v2, i32 %v3) {
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entry:
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%c0 = icmp eq i32 %v0, 0
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%c1 = icmp slt i32 %v1, %v2
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%c2 = icmp sgt i32 %v1, %v2
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%trunc = trunc i32 %v3 to i8
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%sel0 = select i1 %c1, i8 20, i8 %trunc
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%sel1 = select i1 %c2, i8 20, i8 %sel0
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%sel2 = select i1 %c0, i8 %sel1, i8 %sel0
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store volatile i8 %sel2, i8* @g8
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ret void
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}
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