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llvm-mirror/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
Nemanja Ivanovic f6f0a5745d [PowerPC] Canonicalize shuffles to match more single-instruction masks on LE 
We currently miss a number of opportunities to emit single-instruction
VMRG[LH][BHW] instructions for shuffles on little endian subtargets. Although
this in itself is not a huge performance opportunity since loading the permute
vector for a VPERM can always be pulled out of loops, producing such merge
instructions is useful to downstream optimizations.
Since VPERM is essentially opaque to all subsequent optimizations, we want to
avoid it as much as possible. Other permute instructions have semantics that can
be reasoned about much more easily in later optimizations.

This patch does the following:
- Canonicalize shuffles so that the first element comes from the first vector
  (since that's what most of the mask matching functions want)
- Switch the elements that come from splat vectors so that they match the
  corresponding elements from the other vector (to allow for merges)
- Adds debugging messages for when a shuffle is matched to a VPERM so that
  anyone interested in improving this further can get the info for their code

Differential revision: https://reviews.llvm.org/D77448
2020-06-18 21:54:22 -05:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9
define dso_local <16 x i8> @testmrghb(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrghb:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrghb v2, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrghb:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrghb v2, v3, v2
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrghb2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrghb2:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrghb v2, v2, v3
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrghb2:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrghb v2, v2, v3
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 24, i32 8, i32 25, i32 9, i32 26, i32 10, i32 27, i32 11, i32 28, i32 12, i32 29, i32 13, i32 30, i32 14, i32 31, i32 15>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrghh(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrghh:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrghh v2, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrghh:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrghh v2, v3, v2
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrghh2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrghh2:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrghh v2, v2, v3
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrghh2:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrghh v2, v2, v3
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 24, i32 25, i32 8, i32 9, i32 26, i32 27, i32 10, i32 11, i32 28, i32 29, i32 12, i32 13, i32 30, i32 31, i32 14, i32 15>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrglb(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrglb:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrglb:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrglb2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrglb2:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrglb v2, v2, v3
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrglb2:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 0, i32 17, i32 1, i32 18, i32 2, i32 19, i32 3, i32 20, i32 4, i32 21, i32 5, i32 22, i32 6, i32 23, i32 7>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrglh(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrglh:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrglh:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrglh2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrglh2:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrglh v2, v2, v3
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrglh2:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 0, i32 1, i32 18, i32 19, i32 2, i32 3, i32 20, i32 21, i32 4, i32 5, i32 22, i32 23, i32 6, i32 7>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrghw(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrghw:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrghw v2, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrghw:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrghw v2, v3, v2
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrghw2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrghw2:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrghw v2, v2, v3
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrghw2:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrghw v2, v2, v3
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 24, i32 25, i32 26, i32 27, i32 8, i32 9, i32 10, i32 11, i32 28, i32 29, i32 30, i32 31, i32 12, i32 13, i32 14, i32 15>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrglw(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrglw:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrglw:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
ret <16 x i8> %shuffle
}
define dso_local <16 x i8> @testmrglw2(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrglw2:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrglw2:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: blr
entry:
%shuffle = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 16, i32 17, i32 18, i32 19, i32 0, i32 1, i32 2, i32 3, i32 20, i32 21, i32 22, i32 23, i32 4, i32 5, i32 6, i32 7>
ret <16 x i8> %shuffle
}
define dso_local <8 x i16> @testmrglb3(<8 x i8>* nocapture readonly %a) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrglb3:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ld r3, 0(r3)
; CHECK-P8-NEXT: xxlxor v2, v2, v2
; CHECK-P8-NEXT: mtvsrd v3, r3
; CHECK-P8-NEXT: vmrghb v2, v2, v3
; CHECK-P8-NEXT: blr
;
; CHECK-P9-LABEL: testmrglb3:
; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxsd v2, 0(r3)
; CHECK-P9-NEXT: xxlxor v3, v3, v3
; CHECK-P9-NEXT: vmrghb v2, v3, v2
; CHECK-P9-NEXT: blr
entry:
%0 = load <8 x i8>, <8 x i8>* %a, align 8
%1 = zext <8 x i8> %0 to <8 x i16>
ret <8 x i16> %1
}
attributes #0 = { nounwind }
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