mirror of
https://github.com/RPCS3/llvm-mirror.git
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92b6c807c7
llvm-svn: 31331
151 lines
5.1 KiB
C++
151 lines
5.1 KiB
C++
//===-- AlphaLLRP.cpp - Alpha Load Load Replay Trap elimination pass. -- --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Andrew Lenharth and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Here we check for potential replay traps introduced by the spiller
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// We also align some branch targets if we can do so for free
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/ADT/SetOperations.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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namespace {
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Statistic<> nopintro("alpha-nops", "Number of nops inserted");
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Statistic<> nopalign("alpha-nops-align",
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"Number of nops inserted for alignment");
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cl::opt<bool>
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AlignAll("alpha-align-all", cl::Hidden,
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cl::desc("Align all blocks"));
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struct AlphaLLRPPass : public MachineFunctionPass {
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/// Target machine description which we query for reg. names, data
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/// layout, etc.
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///
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AlphaTargetMachine &TM;
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AlphaLLRPPass(AlphaTargetMachine &tm) : TM(tm) { }
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virtual const char *getPassName() const {
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return "Alpha NOP inserter";
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}
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bool runOnMachineFunction(MachineFunction &F) {
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bool Changed = false;
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MachineInstr* prev[3] = {0,0,0};
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unsigned count = 0;
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for (MachineFunction::iterator FI = F.begin(), FE = F.end();
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FI != FE; ++FI) {
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MachineBasicBlock& MBB = *FI;
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bool ub = false;
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
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if (count%4 == 0)
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prev[0] = prev[1] = prev[2] = 0; //Slots cleared at fetch boundary
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++count;
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MachineInstr *MI = I++;
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switch (MI->getOpcode()) {
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case Alpha::LDQ: case Alpha::LDL:
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case Alpha::LDWU: case Alpha::LDBU:
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case Alpha::LDT: case Alpha::LDS:
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case Alpha::STQ: case Alpha::STL:
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case Alpha::STW: case Alpha::STB:
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case Alpha::STT: case Alpha::STS:
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if (MI->getOperand(2).getReg() == Alpha::R30) {
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if (prev[0]
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&& prev[0]->getOperand(2).getReg() ==
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MI->getOperand(2).getReg()
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&& prev[0]->getOperand(1).getImmedValue() ==
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MI->getOperand(1).getImmedValue()) {
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prev[0] = prev[1];
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prev[1] = prev[2];
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prev[2] = 0;
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BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
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.addReg(Alpha::R31);
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Changed = true; nopintro += 1;
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count += 1;
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} else if (prev[1]
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&& prev[1]->getOperand(2).getReg() ==
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MI->getOperand(2).getReg()
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&& prev[1]->getOperand(1).getImmedValue() ==
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MI->getOperand(1).getImmedValue()) {
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prev[0] = prev[2];
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prev[1] = prev[2] = 0;
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BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
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.addReg(Alpha::R31);
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BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
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.addReg(Alpha::R31);
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Changed = true; nopintro += 2;
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count += 2;
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} else if (prev[2]
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&& prev[2]->getOperand(2).getReg() ==
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MI->getOperand(2).getReg()
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&& prev[2]->getOperand(1).getImmedValue() ==
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MI->getOperand(1).getImmedValue()) {
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prev[0] = prev[1] = prev[2] = 0;
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BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
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.addReg(Alpha::R31);
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BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
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.addReg(Alpha::R31);
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BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
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.addReg(Alpha::R31);
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Changed = true; nopintro += 3;
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count += 3;
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}
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prev[0] = prev[1];
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prev[1] = prev[2];
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prev[2] = MI;
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break;
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}
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prev[0] = prev[1];
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prev[1] = prev[2];
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prev[2] = 0;
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break;
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case Alpha::ALTENT:
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case Alpha::MEMLABEL:
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case Alpha::PCLABEL:
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--count;
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break;
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case Alpha::BR:
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case Alpha::JMP:
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ub = true;
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//fall through
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default:
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prev[0] = prev[1];
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prev[1] = prev[2];
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prev[2] = 0;
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break;
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}
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}
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if (ub || AlignAll) {
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//we can align stuff for free at this point
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while (count % 4) {
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BuildMI(MBB, MBB.end(), Alpha::BISr, 2, Alpha::R31)
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.addReg(Alpha::R31).addReg(Alpha::R31);
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++count;
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++nopalign;
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prev[0] = prev[1];
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prev[1] = prev[2];
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prev[2] = 0;
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}
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}
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}
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return Changed;
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}
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};
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} // end of anonymous namespace
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FunctionPass *llvm::createAlphaLLRPPass(AlphaTargetMachine &tm) {
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return new AlphaLLRPPass(tm);
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}
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