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dd18739c8d
Reapply r346374 with the fixes for modules build. Original summary: This change implements assembler parser, code emitter, ELF object writer and disassembler for the MSP430 ISA. Also, more instruction forms are added to the target description. Patch by Michael Skvortsov! llvm-svn: 346948
50 lines
1.3 KiB
LLVM
50 lines
1.3 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
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target triple = "msp430---elf"
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declare void @llvm.va_start(i8*) nounwind
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declare void @llvm.va_end(i8*) nounwind
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declare void @llvm.va_copy(i8*, i8*) nounwind
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define void @va_start(i16 %a, ...) nounwind {
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entry:
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; CHECK-LABEL: va_start:
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; CHECK: sub #2, r1
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%vl = alloca i8*, align 2
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%vl1 = bitcast i8** %vl to i8*
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; CHECK-NEXT: mov r1, [[REG:r[0-9]+]]
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; CHECK-NEXT: add #6, [[REG]]
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; CHECK-NEXT: mov [[REG]], 0(r1)
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call void @llvm.va_start(i8* %vl1)
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call void @llvm.va_end(i8* %vl1)
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ret void
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}
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define i16 @va_arg(i8* %vl) nounwind {
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entry:
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; CHECK-LABEL: va_arg:
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%vl.addr = alloca i8*, align 2
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store i8* %vl, i8** %vl.addr, align 2
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; CHECK: mov r12, [[REG:r[0-9]+]]
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; CHECK-NEXT: incd [[REG]]
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; CHECK-NEXT: mov [[REG]], 0(r1)
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%0 = va_arg i8** %vl.addr, i16
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; CHECK-NEXT: mov 0(r12), r12
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ret i16 %0
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}
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define void @va_copy(i8* %vl) nounwind {
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entry:
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; CHECK-LABEL: va_copy:
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%vl.addr = alloca i8*, align 2
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%vl2 = alloca i8*, align 2
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; CHECK-DAG: mov r12, 2(r1)
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store i8* %vl, i8** %vl.addr, align 2
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%0 = bitcast i8** %vl2 to i8*
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%1 = bitcast i8** %vl.addr to i8*
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; CHECK-DAG: mov r12, 0(r1)
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call void @llvm.va_copy(i8* %0, i8* %1)
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ret void
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}
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