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05f3cb9f0c
This patch adds support for the z13 processor type and its vector facility, and adds MC support for all new instructions provided by that facilily. Apart from defining the new instructions, the main changes are: - Adding VR128, VR64 and VR32 register classes. - Making FP64 a subclass of VR64 and FP32 a subclass of VR32. - Adding a D(V,B) addressing mode for scatter/gather operations - Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields. Until now all immediate operands have been the same width as the underlying field (hence the assert->return change in decode[SU]ImmOperand). In addition, sys::getHostCPUName is extended to detect running natively on a z13 machine. Based on a patch by Richard Sandiford. llvm-svn: 236520
127 lines
4.2 KiB
C++
127 lines
4.2 KiB
C++
//===-- SystemZSubtarget.h - SystemZ subtarget information -----*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the SystemZ specific subclass of TargetSubtargetInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZSUBTARGET_H
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#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZSUBTARGET_H
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#include "SystemZFrameLowering.h"
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#include "SystemZISelLowering.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZRegisterInfo.h"
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#include "SystemZSelectionDAGInfo.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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#include <string>
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#define GET_SUBTARGETINFO_HEADER
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#include "SystemZGenSubtargetInfo.inc"
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namespace llvm {
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class GlobalValue;
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class StringRef;
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class SystemZSubtarget : public SystemZGenSubtargetInfo {
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virtual void anchor();
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protected:
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bool HasDistinctOps;
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bool HasLoadStoreOnCond;
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bool HasHighWord;
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bool HasFPExtension;
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bool HasPopulationCount;
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bool HasFastSerialization;
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bool HasInterlockedAccess1;
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bool HasMiscellaneousExtensions;
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bool HasTransactionalExecution;
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bool HasProcessorAssist;
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bool HasVector;
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private:
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Triple TargetTriple;
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SystemZInstrInfo InstrInfo;
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SystemZTargetLowering TLInfo;
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SystemZSelectionDAGInfo TSInfo;
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SystemZFrameLowering FrameLowering;
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SystemZSubtarget &initializeSubtargetDependencies(StringRef CPU,
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StringRef FS);
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public:
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SystemZSubtarget(const std::string &TT, const std::string &CPU,
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const std::string &FS, const TargetMachine &TM);
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const TargetFrameLowering *getFrameLowering() const override {
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return &FrameLowering;
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}
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const SystemZInstrInfo *getInstrInfo() const override { return &InstrInfo; }
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const SystemZRegisterInfo *getRegisterInfo() const override {
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return &InstrInfo.getRegisterInfo();
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}
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const SystemZTargetLowering *getTargetLowering() const override {
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return &TLInfo;
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}
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const TargetSelectionDAGInfo *getSelectionDAGInfo() const override {
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return &TSInfo;
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}
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// This is important for reducing register pressure in vector code.
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bool useAA() const override { return true; }
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// Automatically generated by tblgen.
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void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
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// Return true if the target has the distinct-operands facility.
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bool hasDistinctOps() const { return HasDistinctOps; }
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// Return true if the target has the load/store-on-condition facility.
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bool hasLoadStoreOnCond() const { return HasLoadStoreOnCond; }
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// Return true if the target has the high-word facility.
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bool hasHighWord() const { return HasHighWord; }
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// Return true if the target has the floating-point extension facility.
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bool hasFPExtension() const { return HasFPExtension; }
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// Return true if the target has the population-count facility.
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bool hasPopulationCount() const { return HasPopulationCount; }
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// Return true if the target has the fast-serialization facility.
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bool hasFastSerialization() const { return HasFastSerialization; }
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// Return true if the target has interlocked-access facility 1.
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bool hasInterlockedAccess1() const { return HasInterlockedAccess1; }
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// Return true if the target has the miscellaneous-extensions facility.
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bool hasMiscellaneousExtensions() const {
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return HasMiscellaneousExtensions;
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}
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// Return true if the target has the transactional-execution facility.
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bool hasTransactionalExecution() const { return HasTransactionalExecution; }
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// Return true if the target has the processor-assist facility.
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bool hasProcessorAssist() const { return HasProcessorAssist; }
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// Return true if the target has the vector facility.
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bool hasVector() const { return HasVector; }
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// Return true if GV can be accessed using LARL for reloc model RM
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// and code model CM.
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bool isPC32DBLSymbol(const GlobalValue *GV, Reloc::Model RM,
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CodeModel::Model CM) const;
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bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
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};
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} // end namespace llvm
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#endif
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