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8a77999240
mostly based on the ARM AsmParser at this time and is not particularly
functional.
Changed the MBlaze data layout from:
"E-p:32:32-i8:8:8-i16:16:16-i64:32:32-f64:32:32-v64:32:32-v128:32:32-n32"
to:
"E-p:32:32:32-i8:8:8-i16:16:16"
because the MicroBlaze doesn't have i64, f64, v64, or v128 data types.
Cleaned up the MBlaze source code:
1. The floating point register class has been removed. The
MicroBlaze does not have floating point registers. Floating
point values are simply stored in integer registers.
2. Renaming the CPURegs register class to GPR to reflect the
standard naming.
3. Removing a lot of stale code from AsmPrinter after
the conversion to InstPrinter.
4. Simplified sign extended loads by marking them as
expanded in ISelLowering.
llvm-svn: 117054
187 lines
6.8 KiB
TableGen
187 lines
6.8 KiB
TableGen
//===- MBlazeRegisterInfo.td - MBlaze Register defs --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the MicroBlaze register file
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//===----------------------------------------------------------------------===//
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// We have banks of 32 registers each.
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class MBlazeReg<string n> : Register<n> {
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field bits<5> Num;
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let Namespace = "MBlaze";
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}
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// MBlaze CPU Registers
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class MBlazeGPRReg<bits<5> num, string n> : MBlazeReg<n> {
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let Num = num;
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}
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// MBlaze 32-bit (aliased) FPU Registers
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/*
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class FPR<bits<5> num, string n, list<Register> aliases> : MBlazeReg<n> {
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let Num = num;
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let Aliases = aliases;
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}
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*/
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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let Namespace = "MBlaze" in {
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// General Purpose Registers
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def R0 : MBlazeGPRReg< 0, "r0">, DwarfRegNum<[0]>;
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def R1 : MBlazeGPRReg< 1, "r1">, DwarfRegNum<[1]>;
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def R2 : MBlazeGPRReg< 2, "r2">, DwarfRegNum<[2]>;
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def R3 : MBlazeGPRReg< 3, "r3">, DwarfRegNum<[3]>;
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def R4 : MBlazeGPRReg< 4, "r4">, DwarfRegNum<[5]>;
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def R5 : MBlazeGPRReg< 5, "r5">, DwarfRegNum<[5]>;
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def R6 : MBlazeGPRReg< 6, "r6">, DwarfRegNum<[6]>;
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def R7 : MBlazeGPRReg< 7, "r7">, DwarfRegNum<[7]>;
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def R8 : MBlazeGPRReg< 8, "r8">, DwarfRegNum<[8]>;
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def R9 : MBlazeGPRReg< 9, "r9">, DwarfRegNum<[9]>;
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def R10 : MBlazeGPRReg< 10, "r10">, DwarfRegNum<[10]>;
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def R11 : MBlazeGPRReg< 11, "r11">, DwarfRegNum<[11]>;
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def R12 : MBlazeGPRReg< 12, "r12">, DwarfRegNum<[12]>;
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def R13 : MBlazeGPRReg< 13, "r13">, DwarfRegNum<[13]>;
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def R14 : MBlazeGPRReg< 14, "r14">, DwarfRegNum<[14]>;
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def R15 : MBlazeGPRReg< 15, "r15">, DwarfRegNum<[15]>;
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def R16 : MBlazeGPRReg< 16, "r16">, DwarfRegNum<[16]>;
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def R17 : MBlazeGPRReg< 17, "r17">, DwarfRegNum<[17]>;
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def R18 : MBlazeGPRReg< 18, "r18">, DwarfRegNum<[18]>;
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def R19 : MBlazeGPRReg< 19, "r19">, DwarfRegNum<[19]>;
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def R20 : MBlazeGPRReg< 20, "r20">, DwarfRegNum<[20]>;
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def R21 : MBlazeGPRReg< 21, "r21">, DwarfRegNum<[21]>;
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def R22 : MBlazeGPRReg< 22, "r22">, DwarfRegNum<[22]>;
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def R23 : MBlazeGPRReg< 23, "r23">, DwarfRegNum<[23]>;
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def R24 : MBlazeGPRReg< 24, "r24">, DwarfRegNum<[24]>;
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def R25 : MBlazeGPRReg< 25, "r25">, DwarfRegNum<[25]>;
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def R26 : MBlazeGPRReg< 26, "r26">, DwarfRegNum<[26]>;
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def R27 : MBlazeGPRReg< 27, "r27">, DwarfRegNum<[27]>;
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def R28 : MBlazeGPRReg< 28, "r28">, DwarfRegNum<[28]>;
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def R29 : MBlazeGPRReg< 29, "r29">, DwarfRegNum<[29]>;
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def R30 : MBlazeGPRReg< 30, "r30">, DwarfRegNum<[30]>;
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def R31 : MBlazeGPRReg< 31, "r31">, DwarfRegNum<[31]>;
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/// MBlaze Single point precision FPU Registers
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/*
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def F0 : FPR< 0, "f0", [R0]>, DwarfRegNum<[32]>;
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def F1 : FPR< 1, "f1", [R1]>, DwarfRegNum<[33]>;
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def F2 : FPR< 2, "f2", [R2]>, DwarfRegNum<[34]>;
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def F3 : FPR< 3, "f3", [R3]>, DwarfRegNum<[35]>;
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def F4 : FPR< 4, "f4", [R4]>, DwarfRegNum<[36]>;
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def F5 : FPR< 5, "f5", [R5]>, DwarfRegNum<[37]>;
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def F6 : FPR< 6, "f6", [R6]>, DwarfRegNum<[38]>;
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def F7 : FPR< 7, "f7", [R7]>, DwarfRegNum<[39]>;
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def F8 : FPR< 8, "f8", [R8]>, DwarfRegNum<[40]>;
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def F9 : FPR< 9, "f9", [R9]>, DwarfRegNum<[41]>;
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def F10 : FPR<10, "f10", [R10]>, DwarfRegNum<[42]>;
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def F11 : FPR<11, "f11", [R11]>, DwarfRegNum<[43]>;
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def F12 : FPR<12, "f12", [R12]>, DwarfRegNum<[44]>;
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def F13 : FPR<13, "f13", [R13]>, DwarfRegNum<[45]>;
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def F14 : FPR<14, "f14", [R14]>, DwarfRegNum<[46]>;
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def F15 : FPR<15, "f15", [R15]>, DwarfRegNum<[47]>;
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def F16 : FPR<16, "f16", [R16]>, DwarfRegNum<[48]>;
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def F17 : FPR<17, "f17", [R17]>, DwarfRegNum<[49]>;
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def F18 : FPR<18, "f18", [R18]>, DwarfRegNum<[50]>;
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def F19 : FPR<19, "f19", [R19]>, DwarfRegNum<[51]>;
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def F20 : FPR<20, "f20", [R20]>, DwarfRegNum<[52]>;
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def F21 : FPR<21, "f21", [R21]>, DwarfRegNum<[53]>;
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def F22 : FPR<22, "f22", [R22]>, DwarfRegNum<[54]>;
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def F23 : FPR<23, "f23", [R23]>, DwarfRegNum<[55]>;
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def F24 : FPR<24, "f24", [R24]>, DwarfRegNum<[56]>;
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def F25 : FPR<25, "f25", [R25]>, DwarfRegNum<[57]>;
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def F26 : FPR<26, "f26", [R26]>, DwarfRegNum<[58]>;
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def F27 : FPR<27, "f27", [R27]>, DwarfRegNum<[59]>;
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def F28 : FPR<28, "f28", [R28]>, DwarfRegNum<[60]>;
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def F29 : FPR<29, "f29", [R29]>, DwarfRegNum<[61]>;
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def F30 : FPR<30, "f30", [R30]>, DwarfRegNum<[62]>;
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def F31 : FPR<31, "f31", [R31]>, DwarfRegNum<[63]>;
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*/
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}
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//===----------------------------------------------------------------------===//
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// Register Classes
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//===----------------------------------------------------------------------===//
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def GPR : RegisterClass<"MBlaze", [i32,f32], 32,
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[
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// Return Values and Arguments
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R3, R4, R5, R6, R7, R8, R9, R10,
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// Not preserved across procedure calls
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R11, R12,
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// Callee save
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R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31,
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// Reserved
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R0, // Always zero
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R1, // The stack pointer
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R2, // Read-only small data area anchor
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R13, // Read-write small data area anchor
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R14, // Return address for interrupts
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R15, // Return address for sub-routines
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R16, // Return address for trap
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R17, // Return address for exceptions
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R18, // Reserved for assembler
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R19 // The frame-pointer
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]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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GPRClass::iterator
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GPRClass::allocation_order_end(const MachineFunction &MF) const {
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// The last 10 registers on the list above are reserved
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return end()-10;
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}
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}];
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}
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/*
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def FGR32 : RegisterClass<"MBlaze", [f32], 32,
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[
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// Return Values and Arguments
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F3, F4, F5, F6, F7, F8, F9, F10,
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// Not preserved across procedure calls
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F11, F12,
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// Callee save
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F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, F31,
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// Reserved
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F0, // Always zero
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F1, // The stack pointer
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F2, // Read-only small data area anchor
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F13, // Read-write small data area anchor
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F14, // Return address for interrupts
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F15, // Return address for sub-routines
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F16, // Return address for trap
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F17, // Return address for exceptions
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F18, // Reserved for assembler
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F19 // The frame pointer
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]>
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{
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let MethodProtos = [{
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iterator allocation_order_end(const MachineFunction &MF) const;
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}];
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let MethodBodies = [{
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FGR32Class::iterator
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FGR32Class::allocation_order_end(const MachineFunction &MF) const {
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// The last 10 registers on the list above are reserved
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return end()-10;
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}
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}];
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}
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*/
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