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c67fd5b3a4
AArch64 was asserting when it was asked to provide a register-bank of a size it couldn't deal with (in this case an s128 IMPLICIT_DEF). But we want a robust fallback path so this isn't allowed. llvm-svn: 294248
120 lines
3.9 KiB
C++
120 lines
3.9 KiB
C++
//===- AArch64RegisterBankInfo -----------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the RegisterBankInfo class for AArch64.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64REGISTERBANKINFO_H
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#define GET_REGBANK_DECLARATIONS
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#include "AArch64GenRegisterBank.inc"
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namespace llvm {
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class TargetRegisterInfo;
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class AArch64GenRegisterBankInfo : public RegisterBankInfo {
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protected:
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enum PartialMappingIdx {
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PMI_None = -1,
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PMI_FPR32 = 1,
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PMI_FPR64,
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PMI_FPR128,
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PMI_FPR256,
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PMI_FPR512,
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PMI_GPR32,
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PMI_GPR64,
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PMI_FirstGPR = PMI_GPR32,
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PMI_LastGPR = PMI_GPR64,
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PMI_FirstFPR = PMI_FPR32,
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PMI_LastFPR = PMI_FPR512,
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PMI_Min = PMI_FirstFPR,
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};
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static RegisterBankInfo::PartialMapping PartMappings[];
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static RegisterBankInfo::ValueMapping ValMappings[];
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static PartialMappingIdx BankIDToCopyMapIdx[];
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enum ValueMappingIdx {
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InvalidIdx = 0,
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First3OpsIdx = 1,
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Last3OpsIdx = 19,
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DistanceBetweenRegBanks = 3,
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FirstCrossRegCpyIdx = 22,
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LastCrossRegCpyIdx = 34,
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DistanceBetweenCrossRegCpy = 2
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};
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static bool checkPartialMap(unsigned Idx, unsigned ValStartIdx,
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unsigned ValLength, const RegisterBank &RB);
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static bool checkValueMapImpl(unsigned Idx, unsigned FirstInBank,
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unsigned Size, unsigned Offset);
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static bool checkPartialMappingIdx(PartialMappingIdx FirstAlias,
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PartialMappingIdx LastAlias,
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ArrayRef<PartialMappingIdx> Order);
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static unsigned getRegBankBaseIdxOffset(unsigned RBIdx, unsigned Size);
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/// Get the pointer to the ValueMapping representing the RegisterBank
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/// at \p RBIdx with a size of \p Size.
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///
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/// The returned mapping works for instructions with the same kind of
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/// operands for up to 3 operands.
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///
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/// \pre \p RBIdx != PartialMappingIdx::None
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static const RegisterBankInfo::ValueMapping *
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getValueMapping(PartialMappingIdx RBIdx, unsigned Size);
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/// Get the pointer to the ValueMapping of the operands of a copy
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/// instruction from the \p SrcBankID register bank to the \p DstBankID
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/// register bank with a size of \p Size.
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static const RegisterBankInfo::ValueMapping *
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getCopyMapping(unsigned DstBankID, unsigned SrcBankID, unsigned Size);
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#define GET_TARGET_REGBANK_CLASS
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#include "AArch64GenRegisterBank.inc"
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};
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/// This class provides the information for the target register banks.
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class AArch64RegisterBankInfo final : public AArch64GenRegisterBankInfo {
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/// See RegisterBankInfo::applyMapping.
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void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
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/// Get an instruction mapping where all the operands map to
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/// the same register bank and have similar size.
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///
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/// \pre MI.getNumOperands() <= 3
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///
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/// \return An InstructionMappings with a statically allocated
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/// OperandsMapping.
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static InstructionMapping
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getSameKindOfOperandsMapping(const MachineInstr &MI);
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public:
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AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
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unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
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unsigned Size) const override;
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const RegisterBank &
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getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
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InstructionMappings
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getInstrAlternativeMappings(const MachineInstr &MI) const override;
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InstructionMapping getInstrMapping(const MachineInstr &MI) const override;
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};
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} // End llvm namespace.
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#endif
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