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266 lines
9.4 KiB
C++
266 lines
9.4 KiB
C++
//===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Andrew Lenharth and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for Alpha,
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// converting from a legalized dag to a Alpha dag.
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//
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//===----------------------------------------------------------------------===//
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#include "Alpha.h"
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#include "AlphaTargetMachine.h"
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#include "AlphaISelLowering.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Constants.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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namespace {
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//===--------------------------------------------------------------------===//
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/// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
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/// instructions for SelectionDAG operations.
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///
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class AlphaDAGToDAGISel : public SelectionDAGISel {
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AlphaTargetLowering AlphaLowering;
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public:
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AlphaDAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(AlphaLowering), AlphaLowering(TM) {}
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/// getI64Imm - Return a target constant with the specified value, of type
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/// i64.
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inline SDOperand getI64Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i64);
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}
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virtual bool runOnFunction(Function &Fn) {
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return SelectionDAGISel::runOnFunction(Fn);
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand Select(SDOperand Op);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual const char *getPassName() const {
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return "Alpha DAG->DAG Pattern Instruction Selection";
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}
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// Include the pieces autogenerated from the target description.
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#include "AlphaGenDAGISel.inc"
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private:
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};
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// The selection process is inherently a bottom-up recursive process (users
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// select their uses before themselves). Given infinite stack space, we
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// could just start selecting on the root and traverse the whole graph. In
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// practice however, this causes us to run out of stack space on large basic
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// blocks. To avoid this problem, select the entry node, then all its uses,
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// iteratively instead of recursively.
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std::vector<SDOperand> Worklist;
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Worklist.push_back(DAG.getEntryNode());
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// Note that we can do this in the Alpha target (scanning forward across token
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// chain edges) because no nodes ever get folded across these edges. On a
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// target like X86 which supports load/modify/store operations, this would
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// have to be more careful.
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while (!Worklist.empty()) {
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SDOperand Node = Worklist.back();
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Worklist.pop_back();
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// Chose from the least deep of the top two nodes.
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if (!Worklist.empty() &&
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Worklist.back().Val->getNodeDepth() < Node.Val->getNodeDepth())
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std::swap(Worklist.back(), Node);
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if ((Node.Val->getOpcode() >= ISD::BUILTIN_OP_END &&
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Node.Val->getOpcode() < AlphaISD::FIRST_NUMBER) ||
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CodeGenMap.count(Node)) continue;
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for (SDNode::use_iterator UI = Node.Val->use_begin(),
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E = Node.Val->use_end(); UI != E; ++UI) {
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// Scan the values. If this use has a value that is a token chain, add it
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// to the worklist.
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SDNode *User = *UI;
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for (unsigned i = 0, e = User->getNumValues(); i != e; ++i)
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if (User->getValueType(i) == MVT::Other) {
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Worklist.push_back(SDOperand(User, i));
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break;
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}
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}
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// Finally, legalize this node.
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Select(Node);
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}
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// Select target instructions for the DAG.
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DAG.setRoot(Select(DAG.getRoot()));
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CodeGenMap.clear();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
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N->getOpcode() < AlphaISD::FIRST_NUMBER)
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return Op; // Already selected.
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// If this has already been converted, use it.
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std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
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if (CGMI != CodeGenMap.end()) return CGMI->second;
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switch (N->getOpcode()) {
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default: break;
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case ISD::DYNAMIC_STACKALLOC:
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case ISD::ADD_PARTS:
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case ISD::SUB_PARTS:
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case ISD::SETCC:
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case ISD::CALL:
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case ISD::TAILCALL:
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assert(0 && "You want these too?");
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case ISD::TokenFactor: {
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SDOperand New;
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if (N->getNumOperands() == 2) {
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SDOperand Op0 = Select(N->getOperand(0));
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SDOperand Op1 = Select(N->getOperand(1));
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New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
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} else {
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std::vector<SDOperand> Ops;
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
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Ops.push_back(Select(N->getOperand(i)));
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New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
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}
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CodeGenMap[Op] = New;
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return New;
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}
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case ISD::CopyFromReg: {
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SDOperand Chain = Select(N->getOperand(0));
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if (Chain == N->getOperand(0)) return Op; // No change
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SDOperand New = CurDAG->getCopyFromReg(Chain,
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cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
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return New.getValue(Op.ResNo);
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}
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case ISD::CopyToReg: {
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand Reg = N->getOperand(1);
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SDOperand Val = Select(N->getOperand(2));
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SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
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Chain, Reg, Val);
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CodeGenMap[Op] = New;
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return New;
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}
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case ISD::UNDEF:
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if (N->getValueType(0) == MVT::i64)
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CurDAG->SelectNodeTo(N, Alpha::IDEF, MVT::i64);
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// else if (N->getValueType(0) == MVT::f32)
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// CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F4, MVT::f32);
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// else
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// CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_F8, MVT::f64);
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return SDOperand(N, 0);
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case ISD::FrameIndex: {
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// int FI = cast<FrameIndexSDNode>(N)->getIndex();
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// CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
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// CurDAG->getTargetFrameIndex(FI, MVT::i32),
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// getI32Imm(0));
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// return SDOperand(N, 0);
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assert(0 && "Frame?, you are suppose to look through the window, not at the frame!");
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}
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case ISD::ConstantPool: {
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// Constant *C = cast<ConstantPoolSDNode>(N)->get();
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// SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32);
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// if (PICEnabled)
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// Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI);
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// else
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// Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI);
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// CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI);
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// return SDOperand(N, 0);
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assert(0 && "Constants are overrated");
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}
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case ISD::GlobalAddress: {
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// GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
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// SDOperand Tmp;
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// SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32);
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// if (PICEnabled)
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// Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA);
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// else
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// Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA);
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// if (GV->hasWeakLinkage() || GV->isExternal())
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// CurDAG->SelectNodeTo(N, PPC::LWZ, MVT::i32, GA, Tmp);
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// else
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// CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, GA);
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// return SDOperand(N, 0);
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assert(0 && "GlobalAddresses are for wimps");
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}
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case ISD::CALLSEQ_START:
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case ISD::CALLSEQ_END: {
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unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue();
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unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ?
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Alpha::ADJUSTSTACKDOWN : Alpha::ADJUSTSTACKUP;
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CurDAG->SelectNodeTo(N, Opc, MVT::Other,
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getI64Imm(Amt), Select(N->getOperand(0)));
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return SDOperand(N, 0);
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}
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case ISD::RET: {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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if (N->getNumOperands() == 2) {
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SDOperand Val = Select(N->getOperand(1));
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if (N->getOperand(1).getValueType() == MVT::i64) {
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Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val);
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}
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}
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//BuildMI(BB, Alpha::RET, 2, Alpha::R31).addReg(Alpha::R26).addImm(1);
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// FIXME: add restoring of the RA to R26 to the chain
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// Finally, select this to a ret instruction.
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CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain);
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return SDOperand(N, 0);
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}
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}
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return SelectCode(Op);
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}
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/// createAlphaISelDag - This pass converts a legalized DAG into a
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/// Alpha-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
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return new AlphaDAGToDAGISel(TM);
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}
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