Matt Arsenault 3cd3307a93 AMDGPU/GlobalISel: Regenerate some checks ... Fixes indentation confusing diff in future patch.		2020-11-13 11:29:15 -05:00
..
AArch64	[SVE][CodeGen] Improve codegen of scalable masked scatters	2020-11-13 11:19:36 +00:00
AMDGPU	AMDGPU/GlobalISel: Regenerate some checks	2020-11-13 11:29:15 -05:00
ARC
ARM	[ARM] Fix PR 47980: Use constrainRegClass during foldImmediate opt.	2020-11-10 13:38:11 -08:00
AVR
BPF	[NewPM] Provide method to run all pipeline callbacks, used for -O0	2020-11-11 15:10:27 -08:00
Generic	Revert "[AsmPrinter] fix -disable-debug-info option"	2020-11-13 13:46:13 +01:00
Hexagon
Inputs
Lanai
Mips	[MC][mips] Remove unused check prefixes. NFC	2020-11-13 14:31:13 +03:00
MIR	Revert "Revert "[AMDGPU] Reorganize GCN subtarget features for unaligned access""	2020-11-11 14:40:14 +00:00
MSP430
NVPTX
PowerPC	[PowerPC] Add test case for negated abs. NFC.	2020-11-13 08:06:31 +00:00
RISCV	[RISCV] Add an ANDI to shift amount of FSL/FSR instructions	2020-11-12 07:33:40 -08:00
SPARC	[Sparc] fp16-promote.ll - Refactor check prefixes + remove unused ones	2020-11-11 18:38:22 +00:00
SystemZ	[SystemZ] Regenerate some fp tests + remove unused check prefixes	2020-11-11 18:38:22 +00:00
Thumb
Thumb2	[ARM] Ensure CountReg definition dominates InsertPt when creating t2DoLoopStartTP	2020-11-12 13:47:46 +00:00
VE	[VE] Add vst intrinsic instructions	2020-11-13 19:11:57 +09:00
WebAssembly	[WebAssembly] Add new relocation type for TLS data symbols	2020-11-13 07:59:29 -08:00
WinCFGuard	Revert "Reland [CFGuard] Add address-taken IAT tables and delay-load support"	2020-11-11 16:03:33 +01:00
WinEH
X86	[X86] When storing v1i1/v2i1/v4i1 to memory, make sure we store zeros in the rest of the byte	2020-11-12 21:28:18 -08:00
XCore