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194f00554e
Summary: Implement custom lowering of SHL_PARTS to enable lowering of left shift with larger than 32-bit shifts. Reviewers: eliben, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27232 llvm-svn: 288541
25 lines
807 B
LLVM
25 lines
807 B
LLVM
; RUN: llc < %s -mtriple=lanai-unknown-unknown | FileCheck %s
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; Test left-shift i64 lowering does not result in call being inserted.
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; CHECK-LABEL: shift
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; CHECKT: bt __ashldi3
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; CHECK: or %r0, 0x0, %r[[T0:[0-9]+]]
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; CHECK: mov 0x20, %r[[T1:[0-9]+]]
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; CHECK: sub %r[[T1]], %r[[ShAmt:[0-9]+]], %r[[T1]]
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; CHECK: sub %r0, %r[[T1]], %r[[T1]]
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; CHECK: sh %r[[ShOpB:[0-9]+]], %r[[T1]], %r[[T1]]
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; CHECK: sub.f %r[[ShAmt]], 0x0, %r0
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; CHECK: sel.eq %r0, %r[[T1]], %r[[T1]]
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; CHECK: sh %r[[ShOpA:[0-9]+]], %r[[ShAmt]], %r[[T2:[0-9]+]]
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; CHECK: or %r[[T1]], %r[[T2]], %rv
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; CHECK: sub.f %r[[ShAmt]], 0x20, %r[[T1]]
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; CHECK: sh.pl %r[[ShOpB]], %r[[T1]], %rv
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; CHECK: sh.mi %r[[ShOpB]], %r[[ShAmt]], %r[[T0]]
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define i64 @shift(i64 inreg, i32 inreg) {
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%3 = zext i32 %1 to i64
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%4 = shl i64 %0, %3
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ret i64 %4
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}
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