1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/test/MC/Disassembler/AMDGPU
Stanislav Mekhanoshin a006cc60e7 [AMDGPU] Set default op_sel_hi on accvgpr read/write
These are opsel opcodes with op_sel actually being ignored.
As a such op_sel_hi needs to be set to default 1 even though
these bits are ignored. This is compatibility change.

Differential Revision: https://reviews.llvm.org/D91202
2020-11-10 13:07:29 -08:00
..
aperture-regs.ll
atomic-fadd-insts.txt
buf_fmt_packed_d16.txt [AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier 2020-07-24 16:41:03 +03:00
buf_fmt_unpacked_d16.txt [AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier 2020-07-24 16:41:03 +03:00
decode-err.txt
dl-insts.txt
dpp_gfx9.txt
dpp_vi.txt
ds_vi.txt
exp_gfx10.txt
exp_vi.txt
flat_gfx9.txt AMDGPU: Fix global atomic saddr operand class 2020-08-15 12:12:28 -04:00
flat_gfx10.txt
flat_vi.txt
gfx8_dasm_all.txt [AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds 2020-10-29 17:31:59 +00:00
gfx9_dasm_all.txt [AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds 2020-10-29 17:31:59 +00:00
gfx10_dasm_all.txt [AMDGPU] Fix double space in disassembly of ds_gws_sema_* with gds 2020-10-29 17:31:59 +00:00
gfx10_dasm_dpp8.txt [AMDGPU] Use lowercase for subtarget feature names in RUN lines 2020-10-13 09:02:09 +01:00
gfx10_dasm_dpp16.txt [AMDGPU] Use lowercase for subtarget feature names in RUN lines 2020-10-13 09:02:09 +01:00
gfx10_mimg.txt
gfx10-sgpr-max.txt
gfx10-vop2be-literal.txt
gfx1011_dasm_dlops.txt [AMDGPU] Add gfx1033 target 2020-11-03 16:27:48 +00:00
gfx1030_dasm_new.txt [AMDGPU] Add gfx1033 target 2020-11-03 16:27:48 +00:00
lds_direct_gfx9.txt
lit.local.cfg
literal16_vi.txt [AMDGPU][MC] Corrected decoding of 16-bit literals 2020-07-22 17:20:43 +03:00
literal_gfx9.txt
literal_vi.txt
literalv216_gfx10.txt AMDGPU: Don't use 16-bit FP inline constants in integer operands 2020-06-17 19:14:10 -04:00
mac.txt
mad_mix.txt
mai.txt [AMDGPU] Set default op_sel_hi on accvgpr read/write 2020-11-10 13:07:29 -08:00
mimg_vi.txt
mov.txt
mtbuf_gfx10.txt [AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier 2020-07-24 16:41:03 +03:00
mtbuf_vi.txt [AMDGPU][MC] Added support of SP3 syntax for MTBUF format modifier 2020-07-24 16:41:03 +03:00
mubuf_gfx9.txt
mubuf_gfx10.txt
mubuf_vi.txt
nop.txt
null-reg.txt
sdwa_gfx9.txt
sdwa_vi.txt
si-support.txt Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""" 2020-02-13 10:16:06 -08:00
smem_gfx9.txt [AMDGPU][MC][GFX9+] Enabled 21-bit signed offsets for SMEM instructions 2020-05-06 14:13:10 +03:00
smem_vi.txt [AMDGPU][MC][GFX9+] Enabled 21-bit signed offsets for SMEM instructions 2020-05-06 14:13:10 +03:00
smrd_vi.txt
sop1_gfx9.txt
sop1_vi.txt
sop2_gfx9.txt
sop2_gfx10.txt
sop2_vi.txt
sopc_vi.txt
sopk_gfx9.txt
sopk_vi.txt
sopp_vi.txt
trap_gfx9.txt
trap_vi.txt
vcmp-gfx10.txt [MC][Disassembler][AMDGPU] Remove unused check prefix 2020-11-10 13:10:12 +00:00
vcmpx-gfx10.txt
vintrp.txt
vop1_gfx9.txt
vop1_vi.txt
vop1.txt [AMDGPU][MC] Corrected decoding of 16-bit literals 2020-07-22 17:20:43 +03:00
vop2_vi.txt [AMDGPU][MC][GFX8+] Enabled clamp for v_add_u16, v_sub_u16 and v_subrev_u16 2020-05-25 19:55:38 +03:00
vop3_gfx9.txt [AMDGPU] Fix check prefix for VOP3 VI disassembler tests 2020-10-27 18:43:25 +00:00
vop3_vi.txt [AMDGPU] Fix check prefix for VOP3 VI disassembler tests 2020-10-27 18:43:25 +00:00
vop3-literal.txt [AMDGPU][MC] Corrected decoding of 16-bit literals 2020-07-22 17:20:43 +03:00
vopc_vi.txt
wave32.txt
xdl-insts-gfx908.txt
xdl-insts-gfx1011-gfx1012.txt