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69646a28e6
Summary: This patch fixes pr23772 [ARM] r226200 can emit illegal thumb2 instruction: "sub sp, r12, #80". The violation was that SUB and ADD (reg, immediate) instructions can only write to SP if the source register is also SP. So the above instructions was unpredictable. To enforce that the instruction t2(ADD|SUB)ri does not write to SP we now enforce the destination register to be rGPR (That exclude PC and SP). Different than the ARM specification, that defines one instruction that can read from SP, and one that can't, here we inserted one that can't write to SP, and other that can only write to SP as to reuse most of the hard-coded size optimizations. When performing this change, it uncovered that emitting Thumb2 Reg plus Immediate could not emit all variants of ADD SP, SP #imm instructions before so it was refactored to be able to. (see test/CodeGen/Thumb2/mve-stacksplot.mir where we use a subw sp, sp, Imm12 variant ) It also uncovered a disassembly issue of adr.w instructions, that were only written as SUBW instructions (see llvm/test/MC/Disassembler/ARM/thumb2.txt). Reviewers: eli.friedman, dmgreen, carwil, olista01, efriedma, andreadb Reviewed By: efriedma Subscribers: gbedwell, john.brawn, efriedma, ostannard, kristof.beyls, hiraditya, dmgreen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70680
43 lines
703 B
Plaintext
43 lines
703 B
Plaintext
# RUN: llvm-mc -triple=thumbv8 -disassemble < %s | FileCheck %s
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# CHECK: sevl
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# CHECK: sevl.w
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0x50 0xbf
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0xaf 0xf3 0x05 0x80
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# These are the only coprocessor instructions that remain defined in ARMv8
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# (The operations on p10/p11 disassemble into FP/NEON instructions)
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0x00 0xee 0x10 0x0e
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# CHECK: mcr p14
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0x00 0xee 0x10 0x0f
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# CHECK: mcr p15
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0x10 0xee 0x10 0x0e
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# CHECK: mrc p14
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0x10 0xee 0x10 0x0f
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# CHECK: mrc p15
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0x40 0xec 0x00 0x0e
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# CHECK: mcrr p14
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0x40 0xec 0x00 0x0f
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# CHECK: mcrr p15
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0x50 0xec 0x00 0x0e
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# CHECK: mrrc p14
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0x50 0xec 0x00 0x0f
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# CHECK: mrrc p15
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0x80 0xec 0x00 0x0e
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# CHECK: stc p14
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0x90 0xec 0x00 0x0e
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# CHECK: ldc p14
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[0x0f,0xf2,0x00,0x4d]
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# CHECK: adr.w sp, #1024
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