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llvm-mirror/test
Florian Hahn 068181fb4a [SCEV] Support single-cond range check idiom in applyLoopGuards.
This patch extends applyLoopGuards to detect a single-cond range check
idiom that InstCombine generates.

It extends applyLoopGuards to detect conditions of the form
(-C1 + X < C2). InstCombine will create this form when combining two
checks of the form (X u< C2 + C1) and (X >=u C1).

In practice, this enables us to correctly compute a tight trip count
bounds for code as in the function below. InstCombine will fold the
minimum iteration check created by LoopRotate with the user check (< 8).

    void unsigned_check(short *pred, unsigned width) {
        if (width < 8) {
            for (int x = 0; x < width; x++)
                pred[x] = pred[x] * pred[x];
        }
    }

As a consequence, LLVM creates dead vector loops for the code above,
e.g. see https://godbolt.org/z/cb8eTcqET

https://alive2.llvm.org/ce/z/SHHW4d

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D104741
2021-06-25 10:24:40 +01:00
..
Analysis [SCEV] Support single-cond range check idiom in applyLoopGuards. 2021-06-25 10:24:40 +01:00
Assembler IR: Fix use-list-order round-tripping for call and invoke 2021-06-23 12:04:19 -07:00
Bindings
Bitcode [BitcodeReader] Validate Strtab before accessing. 2021-06-22 14:52:16 +01:00
BugPoint
CodeGen [AArch64] Custom lower <4 x i8> loads 2021-06-25 09:53:51 +01:00
DebugInfo [DebugInfo] Enable variadic debug value salvaging 2021-06-24 13:16:29 +01:00
Demangle [Demangle][Rust] Parse dot suffix 2021-06-18 09:29:45 +02:00
Examples
ExecutionEngine [JITLink][MachO] Add missing testcase. 2021-06-13 20:43:49 +10:00
Feature
FileCheck
Instrumentation [hwasan] Respect llvm.asan.globals. 2021-06-23 18:37:00 -07:00
Integer
JitListener
Linker [IR] convert warn-stack-size from module flag to fn attr 2021-06-21 15:09:25 -07:00
LTO LTO: Export functions referenced by non-canonical CFI jump tables 2021-06-08 14:57:43 -07:00
MachineVerifier
MC [MC][ELF] Change SHT_LLVM_CALL_GRAPH_PROFILE relocations from SHT_RELA to SHT_REL 2021-06-24 21:35:48 -07:00
Object [AMDGPU] Add gfx1035 target 2021-06-24 14:32:41 -04:00
ObjectYAML [WebAssembly] Rename event to tag 2021-06-17 20:34:19 -07:00
Other [OpaquePtr] Allow alias to opaque pointer 2021-06-25 11:16:36 +02:00
SafepointIRVerifier
Support
SymbolRewriter
TableGen [TableGen] Fix printing second PC-relative operand 2021-06-23 13:27:37 +07:00
ThinLTO/X86 [LTO] Support new PM in ThinLTOCodeGenerator. 2021-06-09 10:05:14 +01:00
tools [X86] Add description of FXAM instruction 2021-06-25 12:26:51 +07:00
Transforms Revert "[BuildLibCalls/SimplifyLibCalls] Fix attributes on created CallInst instructions." 2021-06-24 19:24:34 -07:00
Unit
Verifier [OpaquePtr] Mangle intrinsics with opaque pointers arguments 2021-06-23 10:52:13 -07:00
YAMLParser
.clang-format
CMakeLists.txt [IRSim] Adding basic implementation of llvm-sim. 2021-06-23 14:38:58 -05:00
lit.cfg.py [IRSim] Adding basic implementation of llvm-sim. 2021-06-23 14:38:58 -05:00
lit.site.cfg.py.in Make lit configs relocatable again after c747b7d1d9a 2021-06-22 15:27:32 -04:00
TestRunner.sh