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378bc328f0
be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
287 lines
9.5 KiB
C++
287 lines
9.5 KiB
C++
//===-- MipsJITInfo.cpp - Implement the Mips JIT Interface ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the JIT interfaces for the Mips target.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsJITInfo.h"
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#include "MipsInstrInfo.h"
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#include "MipsRelocations.h"
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#include "MipsSubtarget.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Memory.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cstdlib>
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using namespace llvm;
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#define DEBUG_TYPE "jit"
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void MipsJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
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unsigned NewAddr = (intptr_t)New;
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unsigned OldAddr = (intptr_t)Old;
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const unsigned NopInstr = 0x0;
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// If the functions are in the same memory segment, insert PC-region branch.
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if ((NewAddr & 0xF0000000) == ((OldAddr + 4) & 0xF0000000)) {
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unsigned *OldInstruction = (unsigned *)Old;
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*OldInstruction = 0x08000000;
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unsigned JTargetAddr = NewAddr & 0x0FFFFFFC;
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JTargetAddr >>= 2;
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*OldInstruction |= JTargetAddr;
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// Insert a NOP.
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OldInstruction++;
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*OldInstruction = NopInstr;
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sys::Memory::InvalidateInstructionCache(Old, 2 * 4);
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} else {
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// We need to clear hint bits from the instruction, in case it is 'jr ra'.
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const unsigned HintMask = 0xFFFFF83F, ReturnSequence = 0x03e00008;
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unsigned* CurrentInstr = (unsigned*)Old;
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unsigned CurrInstrHintClear = (*CurrentInstr) & HintMask;
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unsigned* NextInstr = CurrentInstr + 1;
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unsigned NextInstrHintClear = (*NextInstr) & HintMask;
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// Do absolute jump if there are 2 or more instructions before return from
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// the old function.
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if ((CurrInstrHintClear != ReturnSequence) &&
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(NextInstrHintClear != ReturnSequence)) {
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const unsigned LuiT0Instr = 0x3c080000, AddiuT0Instr = 0x25080000;
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const unsigned JrT0Instr = 0x01000008;
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// lui t0, high 16 bit of the NewAddr
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(*(CurrentInstr++)) = LuiT0Instr | ((NewAddr & 0xffff0000) >> 16);
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// addiu t0, t0, low 16 bit of the NewAddr
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(*(CurrentInstr++)) = AddiuT0Instr | (NewAddr & 0x0000ffff);
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// jr t0
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(*(CurrentInstr++)) = JrT0Instr;
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(*CurrentInstr) = NopInstr;
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sys::Memory::InvalidateInstructionCache(Old, 4 * 4);
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} else {
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// Unsupported case
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report_fatal_error("MipsJITInfo::replaceMachineCodeForFunction");
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}
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}
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}
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/// JITCompilerFunction - This contains the address of the JIT function used to
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/// compile a function lazily.
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static TargetJITInfo::JITCompilerFn JITCompilerFunction;
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// Get the ASMPREFIX for the current host. This is often '_'.
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#ifndef __USER_LABEL_PREFIX__
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#define __USER_LABEL_PREFIX__
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#endif
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#define GETASMPREFIX2(X) #X
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#define GETASMPREFIX(X) GETASMPREFIX2(X)
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#define ASMPREFIX GETASMPREFIX(__USER_LABEL_PREFIX__)
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// CompilationCallback stub - We can't use a C function with inline assembly in
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// it, because the prolog/epilog inserted by GCC won't work for us. Instead,
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// write our own wrapper, which does things our way, so we have complete control
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// over register saving and restoring. This code saves registers, calls
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// MipsCompilationCallbackC and restores registers.
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extern "C" {
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#if defined (__mips__)
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void MipsCompilationCallback();
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asm(
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".text\n"
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".align 2\n"
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".globl " ASMPREFIX "MipsCompilationCallback\n"
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ASMPREFIX "MipsCompilationCallback:\n"
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".ent " ASMPREFIX "MipsCompilationCallback\n"
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".frame $sp, 32, $ra\n"
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".set noreorder\n"
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".cpload $t9\n"
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"addiu $sp, $sp, -64\n"
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".cprestore 16\n"
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// Save argument registers a0, a1, a2, a3, f12, f14 since they may contain
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// stuff for the real target function right now. We have to act as if this
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// whole compilation callback doesn't exist as far as the caller is
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// concerned. We also need to save the ra register since it contains the
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// original return address, and t8 register since it contains the address
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// of the end of function stub.
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"sw $a0, 20($sp)\n"
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"sw $a1, 24($sp)\n"
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"sw $a2, 28($sp)\n"
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"sw $a3, 32($sp)\n"
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"sw $ra, 36($sp)\n"
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"sw $t8, 40($sp)\n"
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"sdc1 $f12, 48($sp)\n"
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"sdc1 $f14, 56($sp)\n"
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// t8 points at the end of function stub. Pass the beginning of the stub
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// to the MipsCompilationCallbackC.
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"addiu $a0, $t8, -16\n"
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"jal " ASMPREFIX "MipsCompilationCallbackC\n"
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"nop\n"
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// Restore registers.
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"lw $a0, 20($sp)\n"
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"lw $a1, 24($sp)\n"
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"lw $a2, 28($sp)\n"
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"lw $a3, 32($sp)\n"
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"lw $ra, 36($sp)\n"
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"lw $t8, 40($sp)\n"
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"ldc1 $f12, 48($sp)\n"
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"ldc1 $f14, 56($sp)\n"
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"addiu $sp, $sp, 64\n"
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// Jump to the (newly modified) stub to invoke the real function.
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"addiu $t8, $t8, -16\n"
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"jr $t8\n"
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"nop\n"
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".set reorder\n"
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".end " ASMPREFIX "MipsCompilationCallback\n"
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);
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#else // host != Mips
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void MipsCompilationCallback() {
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llvm_unreachable(
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"Cannot call MipsCompilationCallback() on a non-Mips arch!");
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}
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#endif
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}
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/// MipsCompilationCallbackC - This is the target-specific function invoked
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/// by the function stub when we did not know the real target of a call.
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/// This function must locate the start of the stub or call site and pass
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/// it into the JIT compiler function.
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extern "C" void MipsCompilationCallbackC(intptr_t StubAddr) {
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// Get the address of the compiled code for this function.
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intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr);
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// Rewrite the function stub so that we don't end up here every time we
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// execute the call. We're replacing the first four instructions of the
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// stub with code that jumps to the compiled function:
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// lui $t9, %hi(NewVal)
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// addiu $t9, $t9, %lo(NewVal)
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// jr $t9
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// nop
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int Hi = ((unsigned)NewVal & 0xffff0000) >> 16;
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if ((NewVal & 0x8000) != 0)
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Hi++;
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int Lo = (int)(NewVal & 0xffff);
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*(intptr_t *)(StubAddr) = 0xf << 26 | 25 << 16 | Hi;
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*(intptr_t *)(StubAddr + 4) = 9 << 26 | 25 << 21 | 25 << 16 | Lo;
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*(intptr_t *)(StubAddr + 8) = 25 << 21 | 8;
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*(intptr_t *)(StubAddr + 12) = 0;
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sys::Memory::InvalidateInstructionCache((void*) StubAddr, 16);
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}
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TargetJITInfo::LazyResolverFn MipsJITInfo::getLazyResolverFunction(
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JITCompilerFn F) {
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JITCompilerFunction = F;
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return MipsCompilationCallback;
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}
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TargetJITInfo::StubLayout MipsJITInfo::getStubLayout() {
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// The stub contains 4 4-byte instructions, aligned at 4 bytes. See
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// emitFunctionStub for details.
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StubLayout Result = { 4*4, 4 };
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return Result;
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}
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void *MipsJITInfo::emitFunctionStub(const Function *F, void *Fn,
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JITCodeEmitter &JCE) {
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JCE.emitAlignment(4);
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void *Addr = (void*) (JCE.getCurrentPCValue());
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if (!sys::Memory::setRangeWritable(Addr, 16))
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llvm_unreachable("ERROR: Unable to mark stub writable.");
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intptr_t EmittedAddr;
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if (Fn != (void*)(intptr_t)MipsCompilationCallback)
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EmittedAddr = (intptr_t)Fn;
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else
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EmittedAddr = (intptr_t)MipsCompilationCallback;
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int Hi = ((unsigned)EmittedAddr & 0xffff0000) >> 16;
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if ((EmittedAddr & 0x8000) != 0)
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Hi++;
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int Lo = (int)(EmittedAddr & 0xffff);
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// lui $t9, %hi(EmittedAddr)
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// addiu $t9, $t9, %lo(EmittedAddr)
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// jalr $t8, $t9
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// nop
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if (IsLittleEndian) {
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JCE.emitWordLE(0xf << 26 | 25 << 16 | Hi);
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JCE.emitWordLE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
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JCE.emitWordLE(25 << 21 | 24 << 11 | 9);
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JCE.emitWordLE(0);
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} else {
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JCE.emitWordBE(0xf << 26 | 25 << 16 | Hi);
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JCE.emitWordBE(9 << 26 | 25 << 21 | 25 << 16 | Lo);
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JCE.emitWordBE(25 << 21 | 24 << 11 | 9);
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JCE.emitWordBE(0);
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}
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sys::Memory::InvalidateInstructionCache(Addr, 16);
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if (!sys::Memory::setRangeExecutable(Addr, 16))
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llvm_unreachable("ERROR: Unable to mark stub executable.");
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return Addr;
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}
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/// relocate - Before the JIT can run a block of code that has been emitted,
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/// it must rewrite the code to contain the actual addresses of any
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/// referenced global symbols.
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void MipsJITInfo::relocate(void *Function, MachineRelocation *MR,
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unsigned NumRelocs, unsigned char *GOTBase) {
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for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
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void *RelocPos = (char*) Function + MR->getMachineCodeOffset();
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intptr_t ResultPtr = (intptr_t) MR->getResultPointer();
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switch ((Mips::RelocationType) MR->getRelocationType()) {
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case Mips::reloc_mips_pc16:
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ResultPtr = (((ResultPtr - (intptr_t) RelocPos) - 4) >> 2) & 0xffff;
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*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
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break;
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case Mips::reloc_mips_26:
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ResultPtr = (ResultPtr & 0x0fffffff) >> 2;
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*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
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break;
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case Mips::reloc_mips_hi:
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ResultPtr = ResultPtr >> 16;
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if ((((intptr_t) (MR->getResultPointer()) & 0xffff) >> 15) == 1) {
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ResultPtr += 1;
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}
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*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
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break;
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case Mips::reloc_mips_lo: {
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// Addend is needed for unaligned load/store instructions, where offset
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// for the second load/store in the expanded instruction sequence must
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// be modified by +1 or +3. Otherwise, Addend is 0.
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int Addend = *((unsigned*) RelocPos) & 0xffff;
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ResultPtr = (ResultPtr + Addend) & 0xffff;
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*((unsigned*) RelocPos) &= 0xffff0000;
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*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
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break;
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}
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}
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}
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}
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