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57c57b7739
The access function has a short entry and a short exit, the initialization block is only run the first time. To improve the performance, we want to have a short frame at the entry and exit. We explicitly handle most of the CSRs via copies. Only the CSRs that are not handled via copies will be in CSR_SaveList. Frame lowering and prologue/epilogue insertion will generate a short frame in the entry and exit according to CSR_SaveList. The majority of the CSRs will be handled by register allcoator. Register allocator will try to spill and reload them in the initialization block. We add CSRsViaCopy, it will be explicitly handled during lowering. 1> we first set FunctionLoweringInfo->SplitCSR if conditions are met (the target supports it for the given machine function and the function has only return exits). We also call TLI->initializeSplitCSR to perform initialization. 2> we call TLI->insertCopiesSplitCSR to insert copies from CSRsViaCopy to virtual registers at beginning of the entry block and copies from virtual registers to CSRsViaCopy at beginning of the exit blocks. 3> we also need to make sure the explicit copies will not be eliminated. The target independent portion was committed as r255353. rdar://problem/23557469 Differential Revision: http://reviews.llvm.org/D15341 llvm-svn: 255821
561 lines
20 KiB
C++
561 lines
20 KiB
C++
//==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that AArch64 uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
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#include "AArch64.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Instruction.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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namespace AArch64ISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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WrapperLarge, // 4-instruction MOVZ/MOVK sequence for 64-bit addresses.
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CALL, // Function call.
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// Produces the full sequence of instructions for getting the thread pointer
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// offset of a variable into X0, using the TLSDesc model.
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TLSDESC_CALLSEQ,
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ADRP, // Page address of a TargetGlobalAddress operand.
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ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.
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LOADgot, // Load from automatically generated descriptor (e.g. Global
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// Offset Table, TLS record).
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RET_FLAG, // Return with a flag operand. Operand 0 is the chain operand.
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BRCOND, // Conditional branch instruction; "b.cond".
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CSEL,
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FCSEL, // Conditional move instruction.
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CSINV, // Conditional select invert.
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CSNEG, // Conditional select negate.
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CSINC, // Conditional select increment.
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// Pointer to the thread's local storage area. Materialised from TPIDR_EL0 on
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// ELF.
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THREAD_POINTER,
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ADC,
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SBC, // adc, sbc instructions
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// Arithmetic instructions which write flags.
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ADDS,
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SUBS,
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ADCS,
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SBCS,
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ANDS,
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// Conditional compares. Operands: left,right,falsecc,cc,flags
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CCMP,
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CCMN,
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FCCMP,
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// Floating point comparison
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FCMP,
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// Scalar extract
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EXTR,
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// Scalar-to-vector duplication
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DUP,
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DUPLANE8,
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DUPLANE16,
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DUPLANE32,
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DUPLANE64,
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// Vector immedate moves
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MOVI,
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MOVIshift,
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MOVIedit,
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MOVImsl,
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FMOV,
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MVNIshift,
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MVNImsl,
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// Vector immediate ops
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BICi,
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ORRi,
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// Vector bit select: similar to ISD::VSELECT but not all bits within an
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// element must be identical.
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BSL,
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// Vector arithmetic negation
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NEG,
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// Vector shuffles
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ZIP1,
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ZIP2,
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UZP1,
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UZP2,
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TRN1,
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TRN2,
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REV16,
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REV32,
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REV64,
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EXT,
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// Vector shift by scalar
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VSHL,
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VLSHR,
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VASHR,
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// Vector shift by scalar (again)
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SQSHL_I,
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UQSHL_I,
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SQSHLU_I,
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SRSHR_I,
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URSHR_I,
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// Vector comparisons
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CMEQ,
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CMGE,
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CMGT,
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CMHI,
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CMHS,
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FCMEQ,
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FCMGE,
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FCMGT,
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// Vector zero comparisons
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CMEQz,
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CMGEz,
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CMGTz,
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CMLEz,
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CMLTz,
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FCMEQz,
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FCMGEz,
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FCMGTz,
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FCMLEz,
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FCMLTz,
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// Vector across-lanes addition
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// Only the lower result lane is defined.
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SADDV,
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UADDV,
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// Vector across-lanes min/max
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// Only the lower result lane is defined.
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SMINV,
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UMINV,
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SMAXV,
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UMAXV,
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// Vector bitwise negation
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NOT,
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// Vector bitwise selection
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BIT,
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// Compare-and-branch
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CBZ,
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CBNZ,
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TBZ,
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TBNZ,
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// Tail calls
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TC_RETURN,
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// Custom prefetch handling
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PREFETCH,
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// {s|u}int to FP within a FP register.
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SITOF,
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UITOF,
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/// Natural vector cast. ISD::BITCAST is not natural in the big-endian
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/// world w.r.t vectors; which causes additional REV instructions to be
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/// generated to compensate for the byte-swapping. But sometimes we do
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/// need to re-interpret the data in SIMD vector registers in big-endian
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/// mode without emitting such REV instructions.
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NVCAST,
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SMULL,
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UMULL,
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// NEON Load/Store with post-increment base updates
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LD2post = ISD::FIRST_TARGET_MEMORY_OPCODE,
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LD3post,
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LD4post,
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ST2post,
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ST3post,
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ST4post,
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LD1x2post,
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LD1x3post,
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LD1x4post,
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ST1x2post,
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ST1x3post,
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ST1x4post,
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LD1DUPpost,
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LD2DUPpost,
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LD3DUPpost,
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LD4DUPpost,
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LD1LANEpost,
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LD2LANEpost,
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LD3LANEpost,
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LD4LANEpost,
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ST2LANEpost,
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ST3LANEpost,
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ST4LANEpost
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};
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} // end namespace AArch64ISD
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class AArch64Subtarget;
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class AArch64TargetMachine;
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class AArch64TargetLowering : public TargetLowering {
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public:
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explicit AArch64TargetLowering(const TargetMachine &TM,
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const AArch64Subtarget &STI);
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/// Selects the correct CCAssignFn for a given CallingConvention value.
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CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
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/// Determine which of the bits specified in Mask are known to be either zero
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/// or one and return them in the KnownZero/KnownOne bitsets.
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void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
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APInt &KnownOne, const SelectionDAG &DAG,
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unsigned Depth = 0) const override;
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MVT getScalarShiftAmountTy(const DataLayout &DL, EVT) const override;
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/// Returns true if the target allows unaligned memory accesses of the
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/// specified type.
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace = 0,
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unsigned Align = 1,
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bool *Fast = nullptr) const override;
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/// Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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const char *getTargetNodeName(unsigned Opcode) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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/// Returns true if a cast between SrcAS and DestAS is a noop.
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bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
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// Addrspacecasts are always noops.
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return true;
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}
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/// This method returns a target specific FastISel object, or null if the
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/// target does not support "fast" ISel.
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FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
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const TargetLibraryInfo *libInfo) const override;
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
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/// Return true if the given shuffle mask can be codegen'd directly, or if it
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/// should be stack expanded.
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bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
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/// Return the ISD::SETCC ValueType.
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
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MachineBasicBlock *EmitF128CSEL(MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *MBB) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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unsigned Intrinsic) const override;
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bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
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bool isTruncateFree(EVT VT1, EVT VT2) const override;
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bool isProfitableToHoist(Instruction *I) const override;
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bool isZExtFree(Type *Ty1, Type *Ty2) const override;
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bool isZExtFree(EVT VT1, EVT VT2) const override;
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bool isZExtFree(SDValue Val, EVT VT2) const override;
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bool hasPairedLoad(Type *LoadedType,
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unsigned &RequiredAligment) const override;
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bool hasPairedLoad(EVT LoadedType, unsigned &RequiredAligment) const override;
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unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
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bool lowerInterleavedLoad(LoadInst *LI,
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ArrayRef<ShuffleVectorInst *> Shuffles,
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ArrayRef<unsigned> Indices,
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unsigned Factor) const override;
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bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
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unsigned Factor) const override;
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bool isLegalAddImmediate(int64_t) const override;
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bool isLegalICmpImmediate(int64_t) const override;
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EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
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bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
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MachineFunction &MF) const override;
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/// Return true if the addressing mode represented by AM is legal for this
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/// target, for a load/store of the specified type.
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS) const override;
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/// \brief Return the cost of the scaling factor used in the addressing
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/// mode represented by AM for this target, for a load/store
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/// of the specified type.
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/// If the AM is supported, the return value must be >= 0.
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/// If the AM is not supported, it returns a negative value.
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int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS) const override;
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/// Return true if an FMA operation is faster than a pair of fmul and fadd
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/// instructions. fmuladd intrinsics will be expanded to FMAs when this method
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/// returns true, otherwise fmuladd is expanded to fmul + fadd.
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bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
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const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
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/// \brief Returns false if N is a bit extraction pattern of (X >> C) & Mask.
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bool isDesirableToCommuteWithShift(const SDNode *N) const override;
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/// \brief Returns true if it is beneficial to convert a load of a constant
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/// to just the constant itself.
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bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
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Type *Ty) const override;
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Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
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AtomicOrdering Ord) const override;
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Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
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Value *Addr, AtomicOrdering Ord) const override;
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void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
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TargetLoweringBase::AtomicExpansionKind
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shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
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bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
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TargetLoweringBase::AtomicExpansionKind
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
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bool useLoadStackGuardNode() const override;
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TargetLoweringBase::LegalizeTypeAction
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getPreferredVectorAction(EVT VT) const override;
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/// If the target has a standard location for the unsafe stack pointer,
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/// returns the address of that location. Otherwise, returns nullptr.
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Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override;
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/// If a physical register, this returns the register that receives the
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/// exception address on entry to an EH pad.
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unsigned
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getExceptionPointerRegister(const Constant *PersonalityFn) const override {
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// FIXME: This is a guess. Has this been defined yet?
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return AArch64::X0;
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}
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/// If a physical register, this returns the register that receives the
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/// exception typeid on entry to a landing pad.
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unsigned
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getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
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// FIXME: This is a guess. Has this been defined yet?
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return AArch64::X1;
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}
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bool isCheapToSpeculateCttz() const override {
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return true;
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}
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bool isCheapToSpeculateCtlz() const override {
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return true;
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}
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bool supportSplitCSR(MachineFunction *MF) const override {
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return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
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MF->getFunction()->hasFnAttribute(Attribute::NoUnwind);
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}
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void initializeSplitCSR(MachineBasicBlock *Entry) const override;
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void insertCopiesSplitCSR(
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MachineBasicBlock *Entry,
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const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
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private:
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bool isExtFreeImpl(const Instruction *Ext) const override;
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/// Keep a pointer to the AArch64Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const AArch64Subtarget *Subtarget;
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void addTypeForNEON(EVT VT, EVT PromotedBitwiseVT);
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void addDRTypeForNEON(MVT VT);
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void addQRTypeForNEON(MVT VT);
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SDValue
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LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
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SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCall(CallLoweringInfo & /*CLI*/,
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SmallVectorImpl<SDValue> &InVals) const override;
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SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL,
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SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
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bool isThisReturn, SDValue ThisVal) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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bool isEligibleForTailCallOptimization(
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SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
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bool isCalleeStructRet, bool isCallerStructRet,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
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/// Finds the incoming stack arguments which overlap the given fixed stack
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/// object and incorporates their load into the current chain. This prevents
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/// an upcoming store from clobbering the stack argument before it's used.
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SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
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MachineFrameInfo *MFI, int ClobberedFI) const;
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bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
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bool IsTailCallConvention(CallingConv::ID CallCC) const;
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void saveVarArgRegisters(CCState &CCInfo, SelectionDAG &DAG, SDLoc DL,
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SDValue &Chain) const;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
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SelectionDAG &DAG) const override;
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SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerELFGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerELFTLSDescCallSeq(SDValue SymAddr, SDLoc DL,
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SelectionDAG &DAG) const;
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SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
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SDValue TVal, SDValue FVal, SDLoc dl,
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SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerAAPCS_VASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerDarwin_VASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVectorSRA_SRL_SHL(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerF128Call(SDValue Op, SelectionDAG &DAG,
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RTLIB::Libcall Call) const;
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SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVectorAND(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerVectorOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
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SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
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std::vector<SDNode *> *Created) const override;
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unsigned combineRepeatedFPDivisors() const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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unsigned getRegisterByName(const char* RegName, EVT VT,
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SelectionDAG &DAG) const override;
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|
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|
/// Examine constraint string and operand type and determine a weight value.
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|
/// The operand object must already have been set up with the operand type.
|
|
ConstraintWeight
|
|
getSingleConstraintMatchWeight(AsmOperandInfo &info,
|
|
const char *constraint) const override;
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|
|
|
std::pair<unsigned, const TargetRegisterClass *>
|
|
getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
|
StringRef Constraint, MVT VT) const override;
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|
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
|
|
std::vector<SDValue> &Ops,
|
|
SelectionDAG &DAG) const override;
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|
|
|
unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
|
|
if (ConstraintCode == "Q")
|
|
return InlineAsm::Constraint_Q;
|
|
// FIXME: clang has code for 'Ump', 'Utf', 'Usa', and 'Ush' but these are
|
|
// followed by llvm_unreachable so we'll leave them unimplemented in
|
|
// the backend for now.
|
|
return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
|
|
}
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|
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bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
|
|
bool mayBeEmittedAsTailCall(CallInst *CI) const override;
|
|
bool getIndexedAddressParts(SDNode *Op, SDValue &Base, SDValue &Offset,
|
|
ISD::MemIndexedMode &AM, bool &IsInc,
|
|
SelectionDAG &DAG) const;
|
|
bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
|
|
ISD::MemIndexedMode &AM,
|
|
SelectionDAG &DAG) const override;
|
|
bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
|
|
SDValue &Offset, ISD::MemIndexedMode &AM,
|
|
SelectionDAG &DAG) const override;
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|
|
|
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
|
|
SelectionDAG &DAG) const override;
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|
|
|
bool functionArgumentNeedsConsecutiveRegisters(Type *Ty,
|
|
CallingConv::ID CallConv,
|
|
bool isVarArg) const override;
|
|
|
|
bool shouldNormalizeToSelectSequence(LLVMContext &, EVT) const override;
|
|
};
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|
|
|
namespace AArch64 {
|
|
FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
|
|
const TargetLibraryInfo *libInfo);
|
|
} // end namespace AArch64
|
|
|
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} // end namespace llvm
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#endif
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