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https://github.com/RPCS3/llvm-mirror.git
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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
407 lines
11 KiB
LLVM
407 lines
11 KiB
LLVM
; RUN: llc < %s -march=arm64 | FileCheck %s
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%struct.X = type { i8, i8, [2 x i8] }
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%struct.Y = type { i32, i8 }
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%struct.Z = type { i8, i8, [2 x i8], i16 }
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%struct.A = type { i64, i8 }
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define void @foo(%struct.X* nocapture %x, %struct.Y* nocapture %y) nounwind optsize ssp {
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; CHECK-LABEL: foo:
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; CHECK: ubfm
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; CHECK-NOT: and
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; CHECK: ret
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%tmp = bitcast %struct.X* %x to i32*
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%tmp1 = load i32* %tmp, align 4
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%b = getelementptr inbounds %struct.Y* %y, i64 0, i32 1
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%bf.clear = lshr i32 %tmp1, 3
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%bf.clear.lobit = and i32 %bf.clear, 1
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%frombool = trunc i32 %bf.clear.lobit to i8
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store i8 %frombool, i8* %b, align 1
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ret void
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}
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define i32 @baz(i64 %cav1.coerce) nounwind {
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; CHECK-LABEL: baz:
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; CHECK: sbfm w0, w0, #0, #3
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%tmp = trunc i64 %cav1.coerce to i32
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%tmp1 = shl i32 %tmp, 28
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%bf.val.sext = ashr exact i32 %tmp1, 28
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ret i32 %bf.val.sext
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}
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define i32 @bar(i64 %cav1.coerce) nounwind {
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; CHECK-LABEL: bar:
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; CHECK: sbfm w0, w0, #4, #9
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%tmp = trunc i64 %cav1.coerce to i32
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%cav1.sroa.0.1.insert = shl i32 %tmp, 22
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%tmp1 = ashr i32 %cav1.sroa.0.1.insert, 26
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ret i32 %tmp1
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}
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define void @fct1(%struct.Z* nocapture %x, %struct.A* nocapture %y) nounwind optsize ssp {
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; CHECK-LABEL: fct1:
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; CHECK: ubfm
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; CHECK-NOT: and
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; CHECK: ret
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%tmp = bitcast %struct.Z* %x to i64*
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%tmp1 = load i64* %tmp, align 4
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%b = getelementptr inbounds %struct.A* %y, i64 0, i32 0
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%bf.clear = lshr i64 %tmp1, 3
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%bf.clear.lobit = and i64 %bf.clear, 1
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store i64 %bf.clear.lobit, i64* %b, align 8
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ret void
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}
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define i64 @fct2(i64 %cav1.coerce) nounwind {
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; CHECK-LABEL: fct2:
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; CHECK: sbfm x0, x0, #0, #35
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%tmp = shl i64 %cav1.coerce, 28
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%bf.val.sext = ashr exact i64 %tmp, 28
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ret i64 %bf.val.sext
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}
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define i64 @fct3(i64 %cav1.coerce) nounwind {
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; CHECK-LABEL: fct3:
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; CHECK: sbfm x0, x0, #4, #41
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%cav1.sroa.0.1.insert = shl i64 %cav1.coerce, 22
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%tmp1 = ashr i64 %cav1.sroa.0.1.insert, 26
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ret i64 %tmp1
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}
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define void @fct4(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct4:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], x1, #16, #39
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; CHECK-NEXT: str [[REG1]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -16777216
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 16777215
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%or = or i64 %and, %and1
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store i64 %or, i64* %y, align 8
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ret void
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}
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define void @fct5(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct5:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], w1, #16, #18
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; CHECK-NEXT: str [[REG1]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -8
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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store i32 %or, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some low bits
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define void @fct6(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct6:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], w1, #16, #18
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; lsr is an alias of ubfm
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; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -8
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%shr1 = lshr i32 %or, 2
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store i32 %shr1, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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define void @fct7(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct7:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], w1, #16, #18
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; lsl is an alias of ubfm
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; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -8
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%shl = shl i32 %or, 2
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store i32 %shl, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some low bits
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; (i64 version)
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define void @fct8(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct8:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], x1, #16, #18
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; lsr is an alias of ubfm
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; CHECK-NEXT: lsr [[REG2:x[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -8
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 7
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%or = or i64 %and, %and1
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%shr1 = lshr i64 %or, 2
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store i64 %shr1, i64* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; (i64 version)
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define void @fct9(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct9:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], x1, #16, #18
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; lsr is an alias of ubfm
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; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -8
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 7
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%or = or i64 %and, %and1
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%shl = shl i64 %or, 2
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store i64 %shl, i64* %y, align 8
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ret void
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}
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; Check if we can catch bfm instruction when lsb is 0 (i.e., no lshr)
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; (i32 version)
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define void @fct10(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct10:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], w1, #0, #2
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; lsl is an alias of ubfm
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; CHECK-NEXT: lsl [[REG2:w[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -8
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%and1 = and i32 %x, 7
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%or = or i32 %and, %and1
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%shl = shl i32 %or, 2
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store i32 %shl, i32* %y, align 8
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ret void
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}
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; Check if we can catch bfm instruction when lsb is 0 (i.e., no lshr)
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; (i64 version)
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define void @fct11(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct11:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], x1, #0, #2
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; lsl is an alias of ubfm
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; CHECK-NEXT: lsl [[REG2:x[0-9]+]], [[REG1]], #2
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -8
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%and1 = and i64 %x, 7
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%or = or i64 %and, %and1
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%shl = shl i64 %or, 2
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store i64 %shl, i64* %y, align 8
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ret void
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}
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define zeroext i1 @fct12bis(i32 %tmp2) unnamed_addr nounwind ssp align 2 {
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; CHECK-LABEL: fct12bis:
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; CHECK-NOT: and
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; CHECK: ubfm w0, w0, #11, #11
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%and.i.i = and i32 %tmp2, 2048
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%tobool.i.i = icmp ne i32 %and.i.i, 0
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ret i1 %tobool.i.i
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits
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define void @fct12(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct12:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], w1, #16, #18
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; lsr is an alias of ubfm
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; CHECK-NEXT: ubfm [[REG2:w[0-9]+]], [[REG1]], #2, #29
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -8
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%shl = shl i32 %or, 2
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%shr2 = lshr i32 %shl, 4
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store i32 %shr2, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits
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; (i64 version)
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define void @fct13(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct13:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], x1, #16, #18
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; lsr is an alias of ubfm
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; CHECK-NEXT: ubfm [[REG2:x[0-9]+]], [[REG1]], #2, #61
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; CHECK-NEXT: str [[REG2]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -8
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 7
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%or = or i64 %and, %and1
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%shl = shl i64 %or, 2
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%shr2 = lshr i64 %shl, 4
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store i64 %shr2, i64* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits
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define void @fct14(i32* nocapture %y, i32 %x, i32 %x1) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct14:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], w1, #16, #23
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; lsr is an alias of ubfm
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; CHECK-NEXT: lsr [[REG2:w[0-9]+]], [[REG1]], #4
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; CHECK-NEXT: bfm [[REG2]], w2, #5, #7
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; lsl is an alias of ubfm
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; CHECK-NEXT: lsl [[REG3:w[0-9]+]], [[REG2]], #2
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; CHECK-NEXT: str [[REG3]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, -256
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 255
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%or = or i32 %and, %and1
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%shl = lshr i32 %or, 4
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%and2 = and i32 %shl, -8
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%shr1 = lshr i32 %x1, 5
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%and3 = and i32 %shr1, 7
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%or1 = or i32 %and2, %and3
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%shl1 = shl i32 %or1, 2
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store i32 %shl1, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits
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; (i64 version)
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define void @fct15(i64* nocapture %y, i64 %x, i64 %x1) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct15:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; CHECK-NEXT: bfm [[REG1]], x1, #16, #23
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; lsr is an alias of ubfm
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; CHECK-NEXT: lsr [[REG2:x[0-9]+]], [[REG1]], #4
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; CHECK-NEXT: bfm [[REG2]], x2, #5, #7
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; lsl is an alias of ubfm
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; CHECK-NEXT: lsl [[REG3:x[0-9]+]], [[REG2]], #2
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; CHECK-NEXT: str [[REG3]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, -256
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 255
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%or = or i64 %and, %and1
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%shl = lshr i64 %or, 4
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%and2 = and i64 %shl, -8
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%shr1 = lshr i64 %x1, 5
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%and3 = and i64 %shr1, 7
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%or1 = or i64 %and2, %and3
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%shl1 = shl i64 %or1, 2
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store i64 %shl1, i64* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits and a masking operation has to be kept
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define void @fct16(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct16:
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; CHECK: ldr [[REG1:w[0-9]+]],
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; Create the constant
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; CHECK: movz [[REGCST:w[0-9]+]], #26, lsl #16
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; CHECK: movk [[REGCST]], #33120
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; Do the masking
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; CHECK: and [[REG2:w[0-9]+]], [[REG1]], [[REGCST]]
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; CHECK-NEXT: bfm [[REG2]], w1, #16, #18
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; lsr is an alias of ubfm
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; CHECK-NEXT: ubfm [[REG3:w[0-9]+]], [[REG2]], #2, #29
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; CHECK-NEXT: str [[REG3]],
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; CHECK-NEXT: ret
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%0 = load i32* %y, align 8
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%and = and i32 %0, 1737056
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%shl = shl i32 %or, 2
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%shr2 = lshr i32 %shl, 4
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store i32 %shr2, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits and a masking operation has to be kept
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; (i64 version)
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define void @fct17(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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entry:
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; CHECK-LABEL: fct17:
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; CHECK: ldr [[REG1:x[0-9]+]],
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; Create the constant
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; CHECK: movz [[REGCST:x[0-9]+]], #26, lsl #16
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; CHECK: movk [[REGCST]], #33120
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; Do the masking
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; CHECK: and [[REG2:x[0-9]+]], [[REG1]], [[REGCST]]
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; CHECK-NEXT: bfm [[REG2]], x1, #16, #18
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; lsr is an alias of ubfm
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; CHECK-NEXT: ubfm [[REG3:x[0-9]+]], [[REG2]], #2, #61
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; CHECK-NEXT: str [[REG3]],
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; CHECK-NEXT: ret
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%0 = load i64* %y, align 8
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%and = and i64 %0, 1737056
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 7
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%or = or i64 %and, %and1
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%shl = shl i64 %or, 2
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%shr2 = lshr i64 %shl, 4
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store i64 %shr2, i64* %y, align 8
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ret void
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}
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define i64 @fct18(i32 %xor72) nounwind ssp {
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; CHECK-LABEL: fct18:
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; CHECK: ubfm x0, x0, #9, #16
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%shr81 = lshr i32 %xor72, 9
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%conv82 = zext i32 %shr81 to i64
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%result = and i64 %conv82, 255
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ret i64 %result
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}
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