mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 03:23:01 +02:00
2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
39 lines
1.2 KiB
LLVM
39 lines
1.2 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
|
|
|
|
; Test load/store of global value from global offset table.
|
|
@seed = common global i64 0, align 8
|
|
|
|
define void @Initrand() nounwind {
|
|
entry:
|
|
; CHECK: @Initrand
|
|
; CHECK: adrp x[[REG:[0-9]+]], _seed@GOTPAGE
|
|
; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed@GOTPAGEOFF]
|
|
; CHECK: str x{{[0-9]+}}, [x[[REG2]]]
|
|
store i64 74755, i64* @seed, align 8
|
|
ret void
|
|
}
|
|
|
|
define i32 @Rand() nounwind {
|
|
entry:
|
|
; CHECK: @Rand
|
|
; CHECK: adrp x[[REG:[0-9]+]], _seed@GOTPAGE
|
|
; CHECK: ldr x[[REG2:[0-9]+]], [x[[REG]], _seed@GOTPAGEOFF]
|
|
; CHECK: movz x[[REG3:[0-9]+]], #1309
|
|
; CHECK: ldr x[[REG4:[0-9]+]], [x[[REG2]]]
|
|
; CHECK: mul x[[REG5:[0-9]+]], x[[REG4]], x[[REG3]]
|
|
; CHECK: movz x[[REG6:[0-9]+]], #13849
|
|
; CHECK: add x[[REG7:[0-9]+]], x[[REG5]], x[[REG6]]
|
|
; CHECK: orr x[[REG8:[0-9]+]], xzr, #0xffff
|
|
; CHECK: and x[[REG9:[0-9]+]], x[[REG7]], x[[REG8]]
|
|
; CHECK: str x[[REG9]], [x[[REG]]]
|
|
; CHECK: ldr x{{[0-9]+}}, [x[[REG]]]
|
|
%0 = load i64* @seed, align 8
|
|
%mul = mul nsw i64 %0, 1309
|
|
%add = add nsw i64 %mul, 13849
|
|
%and = and i64 %add, 65535
|
|
store i64 %and, i64* @seed, align 8
|
|
%1 = load i64* @seed, align 8
|
|
%conv = trunc i64 %1 to i32
|
|
ret i32 %conv
|
|
}
|