mirror of
https://github.com/RPCS3/llvm-mirror.git
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2f13163a84
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
243 lines
8.0 KiB
LLVM
243 lines
8.0 KiB
LLVM
; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
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define <8 x i8> @xtn8b(<8 x i16> %A) nounwind {
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;CHECK-LABEL: xtn8b:
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;CHECK-NOT: ld1
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;CHECK: xtn.8b v0, v0
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;CHECK-NEXT: ret
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%tmp3 = trunc <8 x i16> %A to <8 x i8>
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @xtn4h(<4 x i32> %A) nounwind {
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;CHECK-LABEL: xtn4h:
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;CHECK-NOT: ld1
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;CHECK: xtn.4h v0, v0
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;CHECK-NEXT: ret
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%tmp3 = trunc <4 x i32> %A to <4 x i16>
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @xtn2s(<2 x i64> %A) nounwind {
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;CHECK-LABEL: xtn2s:
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;CHECK-NOT: ld1
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;CHECK: xtn.2s v0, v0
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;CHECK-NEXT: ret
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%tmp3 = trunc <2 x i64> %A to <2 x i32>
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @xtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
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;CHECK-LABEL: xtn2_16b:
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;CHECK-NOT: ld1
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;CHECK: xtn2.16b v0, v1
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;CHECK-NEXT: ret
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%tmp3 = trunc <8 x i16> %A to <8 x i8>
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%res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %res
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}
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define <8 x i16> @xtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
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;CHECK-LABEL: xtn2_8h:
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;CHECK-NOT: ld1
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;CHECK: xtn2.8h v0, v1
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;CHECK-NEXT: ret
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%tmp3 = trunc <4 x i32> %A to <4 x i16>
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%res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %res
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}
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define <4 x i32> @xtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
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;CHECK-LABEL: xtn2_4s:
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;CHECK-NOT: ld1
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;CHECK: xtn2.4s v0, v1
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;CHECK-NEXT: ret
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%tmp3 = trunc <2 x i64> %A to <2 x i32>
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%res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %res
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}
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define <8 x i8> @sqxtn8b(<8 x i16> %A) nounwind {
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;CHECK-LABEL: sqxtn8b:
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;CHECK-NOT: ld1
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;CHECK: sqxtn.8b v0, v0
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;CHECK-NEXT: ret
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%tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtn.v8i8(<8 x i16> %A)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @sqxtn4h(<4 x i32> %A) nounwind {
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;CHECK-LABEL: sqxtn4h:
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;CHECK-NOT: ld1
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;CHECK: sqxtn.4h v0, v0
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;CHECK-NEXT: ret
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%tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtn.v4i16(<4 x i32> %A)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @sqxtn2s(<2 x i64> %A) nounwind {
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;CHECK-LABEL: sqxtn2s:
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;CHECK-NOT: ld1
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;CHECK: sqxtn.2s v0, v0
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;CHECK-NEXT: ret
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%tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtn.v2i32(<2 x i64> %A)
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @sqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
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;CHECK-LABEL: sqxtn2_16b:
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;CHECK-NOT: ld1
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;CHECK: sqxtn2.16b v0, v1
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;CHECK-NEXT: ret
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%tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtn.v8i8(<8 x i16> %A)
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%res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %res
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}
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define <8 x i16> @sqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
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;CHECK-LABEL: sqxtn2_8h:
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;CHECK-NOT: ld1
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;CHECK: sqxtn2.8h v0, v1
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;CHECK-NEXT: ret
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%tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtn.v4i16(<4 x i32> %A)
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%res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %res
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}
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define <4 x i32> @sqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
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;CHECK-LABEL: sqxtn2_4s:
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;CHECK-NOT: ld1
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;CHECK: sqxtn2.4s v0, v1
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;CHECK-NEXT: ret
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%tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtn.v2i32(<2 x i64> %A)
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%res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %res
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}
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declare <8 x i8> @llvm.arm64.neon.sqxtn.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm64.neon.sqxtn.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm64.neon.sqxtn.v2i32(<2 x i64>) nounwind readnone
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define <8 x i8> @uqxtn8b(<8 x i16> %A) nounwind {
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;CHECK-LABEL: uqxtn8b:
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;CHECK-NOT: ld1
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;CHECK: uqxtn.8b v0, v0
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;CHECK-NEXT: ret
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%tmp3 = call <8 x i8> @llvm.arm64.neon.uqxtn.v8i8(<8 x i16> %A)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @uqxtn4h(<4 x i32> %A) nounwind {
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;CHECK-LABEL: uqxtn4h:
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;CHECK-NOT: ld1
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;CHECK: uqxtn.4h v0, v0
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;CHECK-NEXT: ret
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%tmp3 = call <4 x i16> @llvm.arm64.neon.uqxtn.v4i16(<4 x i32> %A)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @uqxtn2s(<2 x i64> %A) nounwind {
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;CHECK-LABEL: uqxtn2s:
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;CHECK-NOT: ld1
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;CHECK: uqxtn.2s v0, v0
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;CHECK-NEXT: ret
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%tmp3 = call <2 x i32> @llvm.arm64.neon.uqxtn.v2i32(<2 x i64> %A)
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @uqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
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;CHECK-LABEL: uqxtn2_16b:
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;CHECK-NOT: ld1
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;CHECK: uqxtn2.16b v0, v1
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;CHECK-NEXT: ret
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%tmp3 = call <8 x i8> @llvm.arm64.neon.uqxtn.v8i8(<8 x i16> %A)
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%res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %res
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}
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define <8 x i16> @uqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
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;CHECK-LABEL: uqxtn2_8h:
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;CHECK-NOT: ld1
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;CHECK: uqxtn2.8h v0, v1
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;CHECK-NEXT: ret
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%tmp3 = call <4 x i16> @llvm.arm64.neon.uqxtn.v4i16(<4 x i32> %A)
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%res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %res
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}
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define <4 x i32> @uqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
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;CHECK-LABEL: uqxtn2_4s:
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;CHECK-NOT: ld1
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;CHECK: uqxtn2.4s v0, v1
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;CHECK-NEXT: ret
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%tmp3 = call <2 x i32> @llvm.arm64.neon.uqxtn.v2i32(<2 x i64> %A)
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%res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %res
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}
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declare <8 x i8> @llvm.arm64.neon.uqxtn.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm64.neon.uqxtn.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm64.neon.uqxtn.v2i32(<2 x i64>) nounwind readnone
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define <8 x i8> @sqxtun8b(<8 x i16> %A) nounwind {
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;CHECK-LABEL: sqxtun8b:
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;CHECK-NOT: ld1
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;CHECK: sqxtun.8b v0, v0
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;CHECK-NEXT: ret
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%tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtun.v8i8(<8 x i16> %A)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @sqxtun4h(<4 x i32> %A) nounwind {
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;CHECK-LABEL: sqxtun4h:
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;CHECK-NOT: ld1
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;CHECK: sqxtun.4h v0, v0
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;CHECK-NEXT: ret
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%tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtun.v4i16(<4 x i32> %A)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @sqxtun2s(<2 x i64> %A) nounwind {
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;CHECK-LABEL: sqxtun2s:
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;CHECK-NOT: ld1
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;CHECK: sqxtun.2s v0, v0
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;CHECK-NEXT: ret
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%tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtun.v2i32(<2 x i64> %A)
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @sqxtun2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind {
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;CHECK-LABEL: sqxtun2_16b:
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;CHECK-NOT: ld1
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;CHECK: sqxtun2.16b v0, v1
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;CHECK-NEXT: ret
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%tmp3 = call <8 x i8> @llvm.arm64.neon.sqxtun.v8i8(<8 x i16> %A)
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%res = shufflevector <8 x i8> %ret, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <16 x i8> %res
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}
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define <8 x i16> @sqxtun2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind {
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;CHECK-LABEL: sqxtun2_8h:
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;CHECK-NOT: ld1
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;CHECK: sqxtun2.8h v0, v1
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;CHECK-NEXT: ret
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%tmp3 = call <4 x i16> @llvm.arm64.neon.sqxtun.v4i16(<4 x i32> %A)
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%res = shufflevector <4 x i16> %ret, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i16> %res
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}
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define <4 x i32> @sqxtun2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind {
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;CHECK-LABEL: sqxtun2_4s:
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;CHECK-NOT: ld1
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;CHECK: sqxtun2.4s v0, v1
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;CHECK-NEXT: ret
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%tmp3 = call <2 x i32> @llvm.arm64.neon.sqxtun.v2i32(<2 x i64> %A)
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%res = shufflevector <2 x i32> %ret, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %res
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}
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declare <8 x i8> @llvm.arm64.neon.sqxtun.v8i8(<8 x i16>) nounwind readnone
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declare <4 x i16> @llvm.arm64.neon.sqxtun.v4i16(<4 x i32>) nounwind readnone
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declare <2 x i32> @llvm.arm64.neon.sqxtun.v2i32(<2 x i64>) nounwind readnone
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