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llvm-mirror/docs/AMDGPU/gfx8_addr_mimg.rst
Dmitry Preobrazhensky ce9abb7e3a [AMDGPU][MC][DOC] Updated AMD GPU assembler description
Stage 2: added detailed description of operands

See bug 36572: https://bugs.llvm.org/show_bug.cgi?id=36572

llvm-svn: 349368
2018-12-17 17:38:11 +00:00

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.. _amdgpu_synid8_addr_mimg:
vaddr
===========================
Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
*Size:* 1, 2, 3, 4, 8 or 16 dwords. Actual size depends on opcode and specific image being handled.
Note 1. Image format and dimensions are encoded in the image resource constant but not in the instruction.
Note 2. Actually image address size may vary from 1 to 13 dwords, but assembler currently supports a limited range of register sequences.
*Operands:* :ref:`v<amdgpu_synid_v>`