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e236141513
Summary: This is a follow-up to r335942. - Merge SISubtarget into AMDGPUSubtarget and rename to GCNSubtarget - Rename AMDGPUCommonSubtarget to AMDGPUSubtarget - Merge R600Subtarget::Generation and GCNSubtarget::Generation into AMDGPUSubtarget::Generation. Reviewers: arsenm, jvesely Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D49037 llvm-svn: 336851
58 lines
1.8 KiB
C++
58 lines
1.8 KiB
C++
//===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// Interface definition for R600RegisterInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
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#define GET_REGINFO_HEADER
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#include "R600GenRegisterInfo.inc"
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namespace llvm {
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struct R600RegisterInfo final : public R600GenRegisterInfo {
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RegClassWeight RCW;
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R600RegisterInfo();
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
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unsigned getFrameRegister(const MachineFunction &MF) const override;
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/// get the HW encoding for a register's channel.
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unsigned getHWRegChan(unsigned reg) const;
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unsigned getHWRegIndex(unsigned Reg) const;
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/// get the register class of the specified type to use in the
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/// CFGStructurizer
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const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
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const RegClassWeight &
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getRegClassWeight(const TargetRegisterClass *RC) const override;
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// \returns true if \p Reg can be defined in one ALU clause and used in
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// another.
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bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS = nullptr) const override;
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void reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const;
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};
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} // End namespace llvm
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#endif
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