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b401fd4c9e
Also avoid locals evicting locals just because they want a cheaper register. Problem: MI Sched knows exactly how many registers we have and assumes they can be colored. In cases where we have large blocks, usually from unrolled loops, greedy coloring fails. This is a source of "regressions" from the MI Scheduler on x86. I noticed this issue on x86 where we have long chains of two-address defs in the same live range. It's easy to see this in matrix multiplication benchmarks like IRSmk and even the unit test misched-matmul.ll. A fundamental difference between the LLVM register allocator and conventional graph coloring is that in our model a live range can't discover its neighbors, it can only verify its neighbors. That's why we initially went for greedy coloring and added eviction to deal with the hard cases. However, for singly defined and two-address live ranges, we can optimally color without visiting neighbors simply by processing the live ranges in instruction order. Other beneficial side effects: It is much easier to understand and debug regalloc for large blocks when the live ranges are allocated in order. Yes, global allocation is still very confusing, but it's nice to be able to comprehend what happened locally. Heuristics could be added to bias register assignment based on instruction locality (think late register pairing, banks...). Intuituvely this will make some test cases that are on the threshold of register pressure more stable. llvm-svn: 187139
80 lines
1.7 KiB
LLVM
80 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=arm -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math | FileCheck %s
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; rdar://7461510
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; rdar://10964603
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; Disable this optimization unless we know one of them is zero.
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define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: vldr [[S0:s[0-9]+]],
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; CHECK: vldr [[S1:s[0-9]+]],
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; CHECK: vcmpe.f32 [[S1]], [[S0]]
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; CHECK: vmrs APSR_nzcv, fpscr
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; CHECK: beq
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%0 = load float* %a
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%1 = load float* %b
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%2 = fcmp une float %0, %1
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br i1 %2, label %bb1, label %bb2
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bb1:
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%3 = call i32 @bar()
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ret i32 %3
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bb2:
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%4 = call i32 @foo()
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ret i32 %4
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}
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; If one side is zero, the other size sign bit is masked off to allow
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; +0.0 == -0.0
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define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK-NOT: vldr
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; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
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; CHECK-NOT: b LBB
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; CHECK: bfc [[REG2]], #31, #1
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; CHECK: cmp [[REG1]], #0
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; CHECK: cmpeq [[REG2]], #0
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; CHECK-NOT: vcmpe.f32
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; CHECK-NOT: vmrs
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; CHECK: bne
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%0 = load double* %a
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%1 = fcmp oeq double %0, 0.000000e+00
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br i1 %1, label %bb1, label %bb2
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bb1:
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%2 = call i32 @bar()
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ret i32 %2
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bb2:
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%3 = call i32 @foo()
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ret i32 %3
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}
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define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK-NOT: vldr
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; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
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; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
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; CHECK: tst [[REG3]], [[REG4]]
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; CHECK-NOT: vcmpe.f32
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; CHECK-NOT: vmrs
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; CHECK: bne
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%0 = load float* %a
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%1 = fcmp oeq float %0, 0.000000e+00
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br i1 %1, label %bb1, label %bb2
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bb1:
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%2 = call i32 @bar()
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ret i32 %2
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bb2:
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%3 = call i32 @foo()
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ret i32 %3
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}
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declare i32 @bar()
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declare i32 @foo()
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