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27693beb8e
There were two problems:
+ AArch64 was reusing random data from its binary op tables, which is
complete nonsense for G_SEQUENCE.
+ Even when AArch64 gave up and said it couldn't handle G_SEQUENCE,
the generic code asserted.
llvm-svn: 288836
578 lines
23 KiB
C++
578 lines
23 KiB
C++
//===- AArch64RegisterBankInfo.cpp -------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the RegisterBankInfo class for
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/// AArch64.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AArch64RegisterBankInfo.h"
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#include "AArch64InstrInfo.h" // For XXXRegClassID.
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
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#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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// This file will be TableGen'ed at some point.
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#include "AArch64GenRegisterBankInfo.def"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
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: RegisterBankInfo(AArch64::RegBanks, AArch64::NumRegisterBanks) {
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static bool AlreadyInit = false;
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// We have only one set of register banks, whatever the subtarget
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// is. Therefore, the initialization of the RegBanks table should be
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// done only once. Indeed the table of all register banks
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// (AArch64::RegBanks) is unique in the compiler. At some point, it
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// will get tablegen'ed and the whole constructor becomes empty.
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if (AlreadyInit)
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return;
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AlreadyInit = true;
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// Initialize the GPR bank.
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createRegisterBank(AArch64::GPRRegBankID, "GPR");
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// The GPR register bank is fully defined by all the registers in
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// GR64all + its subclasses.
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addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI);
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const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
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(void)RBGPR;
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assert(&AArch64::GPRRegBank == &RBGPR &&
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"The order in RegBanks is messed up");
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assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
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"Subclass not added?");
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assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
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// Initialize the FPR bank.
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createRegisterBank(AArch64::FPRRegBankID, "FPR");
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// The FPR register bank is fully defined by all the registers in
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// GR64all + its subclasses.
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addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI);
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const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
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(void)RBFPR;
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assert(&AArch64::FPRRegBank == &RBFPR &&
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"The order in RegBanks is messed up");
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assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
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"Subclass not added?");
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assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
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"Subclass not added?");
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assert(RBFPR.getSize() == 512 &&
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"FPRs should hold up to 512-bit via QQQQ sequence");
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// Initialize the CCR bank.
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createRegisterBank(AArch64::CCRRegBankID, "CCR");
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addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI);
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const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
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(void)RBCCR;
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assert(&AArch64::CCRRegBank == &RBCCR &&
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"The order in RegBanks is messed up");
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assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
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"Class not added?");
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assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");
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// Check that the TableGen'ed like file is in sync we our expectations.
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// First, the Idx.
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assert(AArch64::PartialMappingIdx::PMI_GPR32 ==
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AArch64::PartialMappingIdx::PMI_FirstGPR &&
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"GPR32 index not first in the GPR list");
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assert(AArch64::PartialMappingIdx::PMI_GPR64 ==
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AArch64::PartialMappingIdx::PMI_LastGPR &&
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"GPR64 index not last in the GPR list");
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assert(AArch64::PartialMappingIdx::PMI_FirstGPR <=
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AArch64::PartialMappingIdx::PMI_LastGPR &&
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"GPR list is backward");
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assert(AArch64::PartialMappingIdx::PMI_FPR32 ==
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AArch64::PartialMappingIdx::PMI_FirstFPR &&
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"FPR32 index not first in the FPR list");
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assert(AArch64::PartialMappingIdx::PMI_FPR512 ==
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AArch64::PartialMappingIdx::PMI_LastFPR &&
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"FPR512 index not last in the FPR list");
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assert(AArch64::PartialMappingIdx::PMI_FirstFPR <=
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AArch64::PartialMappingIdx::PMI_LastFPR &&
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"FPR list is backward");
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assert(AArch64::PartialMappingIdx::PMI_FPR32 + 1 ==
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AArch64::PartialMappingIdx::PMI_FPR64 &&
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AArch64::PartialMappingIdx::PMI_FPR64 + 1 ==
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AArch64::PartialMappingIdx::PMI_FPR128 &&
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AArch64::PartialMappingIdx::PMI_FPR128 + 1 ==
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AArch64::PartialMappingIdx::PMI_FPR256 &&
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AArch64::PartialMappingIdx::PMI_FPR256 + 1 ==
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AArch64::PartialMappingIdx::PMI_FPR512 &&
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"FPR indices not properly ordered");
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// Now, the content.
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// Check partial mapping.
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#define CHECK_PARTIALMAP(Idx, ValStartIdx, ValLength, RB) \
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do { \
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const PartialMapping &Map = \
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AArch64::PartMappings[AArch64::PartialMappingIdx::Idx - \
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AArch64::PartialMappingIdx::PMI_Min]; \
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(void)Map; \
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assert(Map.StartIdx == ValStartIdx && Map.Length == ValLength && \
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Map.RegBank == &RB && #Idx " is incorrectly initialized"); \
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} while (0)
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CHECK_PARTIALMAP(PMI_GPR32, 0, 32, RBGPR);
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CHECK_PARTIALMAP(PMI_GPR64, 0, 64, RBGPR);
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CHECK_PARTIALMAP(PMI_FPR32, 0, 32, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR64, 0, 64, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR128, 0, 128, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR256, 0, 256, RBFPR);
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CHECK_PARTIALMAP(PMI_FPR512, 0, 512, RBFPR);
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// Check value mapping.
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#define CHECK_VALUEMAP_IMPL(RBName, Size, Offset) \
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do { \
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unsigned PartialMapBaseIdx = \
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AArch64::PartialMappingIdx::PMI_##RBName##Size - \
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AArch64::PartialMappingIdx::PMI_Min; \
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(void)PartialMapBaseIdx; \
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const ValueMapping &Map = AArch64::getValueMapping( \
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AArch64::PartialMappingIdx::PMI_First##RBName, Size)[Offset]; \
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(void)Map; \
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assert(Map.BreakDown == &AArch64::PartMappings[PartialMapBaseIdx] && \
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Map.NumBreakDowns == 1 && #RBName #Size \
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" " #Offset " is incorrectly initialized"); \
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} while (0)
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#define CHECK_VALUEMAP(RBName, Size) CHECK_VALUEMAP_IMPL(RBName, Size, 0)
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CHECK_VALUEMAP(GPR, 32);
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CHECK_VALUEMAP(GPR, 64);
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CHECK_VALUEMAP(FPR, 32);
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CHECK_VALUEMAP(FPR, 64);
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CHECK_VALUEMAP(FPR, 128);
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CHECK_VALUEMAP(FPR, 256);
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CHECK_VALUEMAP(FPR, 512);
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// Check the value mapping for 3-operands instructions where all the operands
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// map to the same value mapping.
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#define CHECK_VALUEMAP_3OPS(RBName, Size) \
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do { \
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CHECK_VALUEMAP_IMPL(RBName, Size, 0); \
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CHECK_VALUEMAP_IMPL(RBName, Size, 1); \
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CHECK_VALUEMAP_IMPL(RBName, Size, 2); \
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} while (0)
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CHECK_VALUEMAP_3OPS(GPR, 32);
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CHECK_VALUEMAP_3OPS(GPR, 64);
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CHECK_VALUEMAP_3OPS(FPR, 32);
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CHECK_VALUEMAP_3OPS(FPR, 64);
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CHECK_VALUEMAP_3OPS(FPR, 128);
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CHECK_VALUEMAP_3OPS(FPR, 256);
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CHECK_VALUEMAP_3OPS(FPR, 512);
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#define CHECK_VALUEMAP_CROSSREGCPY(RBNameDst, RBNameSrc, Size) \
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do { \
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unsigned PartialMapDstIdx = \
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AArch64::PMI_##RBNameDst##Size - AArch64::PMI_Min; \
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unsigned PartialMapSrcIdx = \
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AArch64::PMI_##RBNameSrc##Size - AArch64::PMI_Min; \
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(void) PartialMapDstIdx; \
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(void) PartialMapSrcIdx; \
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const ValueMapping *Map = AArch64::getCopyMapping( \
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AArch64::PMI_First##RBNameDst == AArch64::PMI_FirstGPR, \
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AArch64::PMI_First##RBNameSrc == AArch64::PMI_FirstGPR, Size); \
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(void) Map; \
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assert(Map[0].BreakDown == &AArch64::PartMappings[PartialMapDstIdx] && \
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Map[0].NumBreakDowns == 1 && #RBNameDst #Size \
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" Dst is incorrectly initialized"); \
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assert(Map[1].BreakDown == &AArch64::PartMappings[PartialMapSrcIdx] && \
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Map[1].NumBreakDowns == 1 && #RBNameSrc #Size \
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" Src is incorrectly initialized"); \
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\
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} while (0)
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CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(GPR, GPR, 64);
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CHECK_VALUEMAP_CROSSREGCPY(GPR, FPR, 64);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 32);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, FPR, 64);
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CHECK_VALUEMAP_CROSSREGCPY(FPR, GPR, 64);
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assert(verify(TRI) && "Invalid register bank information");
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}
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unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A,
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const RegisterBank &B,
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unsigned Size) const {
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// What do we do with different size?
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// copy are same size.
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// Will introduce other hooks for different size:
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// * extract cost.
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// * build_sequence cost.
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// Copy from (resp. to) GPR to (resp. from) FPR involves FMOV.
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// FIXME: This should be deduced from the scheduling model.
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if (&A == &AArch64::GPRRegBank && &B == &AArch64::FPRRegBank)
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// FMOVXDr or FMOVWSr.
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return 5;
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if (&A == &AArch64::FPRRegBank && &B == &AArch64::GPRRegBank)
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// FMOVDXr or FMOVSWr.
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return 4;
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return RegisterBankInfo::copyCost(A, B, Size);
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}
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const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass(
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const TargetRegisterClass &RC) const {
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switch (RC.getID()) {
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case AArch64::FPR8RegClassID:
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case AArch64::FPR16RegClassID:
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case AArch64::FPR32RegClassID:
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case AArch64::FPR64RegClassID:
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case AArch64::FPR128RegClassID:
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case AArch64::FPR128_loRegClassID:
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case AArch64::DDRegClassID:
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case AArch64::DDDRegClassID:
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case AArch64::DDDDRegClassID:
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case AArch64::QQRegClassID:
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case AArch64::QQQRegClassID:
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case AArch64::QQQQRegClassID:
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return getRegBank(AArch64::FPRRegBankID);
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case AArch64::GPR32commonRegClassID:
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case AArch64::GPR32RegClassID:
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case AArch64::GPR32spRegClassID:
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case AArch64::GPR32sponlyRegClassID:
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case AArch64::GPR32allRegClassID:
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case AArch64::GPR64commonRegClassID:
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case AArch64::GPR64RegClassID:
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case AArch64::GPR64spRegClassID:
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case AArch64::GPR64sponlyRegClassID:
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case AArch64::GPR64allRegClassID:
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case AArch64::tcGPR64RegClassID:
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case AArch64::WSeqPairsClassRegClassID:
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case AArch64::XSeqPairsClassRegClassID:
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return getRegBank(AArch64::GPRRegBankID);
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case AArch64::CCRRegClassID:
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return getRegBank(AArch64::CCRRegBankID);
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default:
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llvm_unreachable("Register class not supported");
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}
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}
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RegisterBankInfo::InstructionMappings
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AArch64RegisterBankInfo::getInstrAlternativeMappings(
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const MachineInstr &MI) const {
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const MachineFunction &MF = *MI.getParent()->getParent();
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const TargetSubtargetInfo &STI = MF.getSubtarget();
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const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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switch (MI.getOpcode()) {
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case TargetOpcode::G_OR: {
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// 32 and 64-bit or can be mapped on either FPR or
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// GPR for the same cost.
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unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
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if (Size != 32 && Size != 64)
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break;
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// If the instruction has any implicit-defs or uses,
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// do not mess with it.
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if (MI.getNumOperands() != 3)
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break;
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InstructionMappings AltMappings;
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InstructionMapping GPRMapping(
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/*ID*/ 1, /*Cost*/ 1,
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AArch64::getValueMapping(AArch64::PMI_FirstGPR, Size),
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/*NumOperands*/ 3);
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InstructionMapping FPRMapping(
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/*ID*/ 2, /*Cost*/ 1,
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AArch64::getValueMapping(AArch64::PMI_FirstFPR, Size),
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/*NumOperands*/ 3);
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AltMappings.emplace_back(std::move(GPRMapping));
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AltMappings.emplace_back(std::move(FPRMapping));
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return AltMappings;
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}
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case TargetOpcode::G_BITCAST: {
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unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
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if (Size != 32 && Size != 64)
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break;
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// If the instruction has any implicit-defs or uses,
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// do not mess with it.
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if (MI.getNumOperands() != 2)
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break;
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InstructionMappings AltMappings;
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InstructionMapping GPRMapping(
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/*ID*/ 1, /*Cost*/ 1,
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AArch64::getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ true, Size),
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/*NumOperands*/ 2);
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InstructionMapping FPRMapping(
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/*ID*/ 2, /*Cost*/ 1,
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AArch64::getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ false, Size),
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/*NumOperands*/ 2);
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InstructionMapping GPRToFPRMapping(
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/*ID*/ 3,
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/*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
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AArch64::getCopyMapping(/*DstIsGPR*/ false, /*SrcIsGPR*/ true, Size),
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/*NumOperands*/ 2);
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InstructionMapping FPRToGPRMapping(
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/*ID*/ 3,
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/*Cost*/ copyCost(AArch64::GPRRegBank, AArch64::FPRRegBank, Size),
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AArch64::getCopyMapping(/*DstIsGPR*/ true, /*SrcIsGPR*/ false, Size),
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/*NumOperands*/ 2);
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AltMappings.emplace_back(std::move(GPRMapping));
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AltMappings.emplace_back(std::move(FPRMapping));
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AltMappings.emplace_back(std::move(GPRToFPRMapping));
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AltMappings.emplace_back(std::move(FPRToGPRMapping));
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return AltMappings;
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}
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case TargetOpcode::G_LOAD: {
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unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
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if (Size != 64)
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break;
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// If the instruction has any implicit-defs or uses,
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// do not mess with it.
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if (MI.getNumOperands() != 2)
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break;
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InstructionMappings AltMappings;
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InstructionMapping GPRMapping(
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/*ID*/ 1, /*Cost*/ 1,
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getOperandsMapping(
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{AArch64::getValueMapping(AArch64::PMI_FirstGPR, Size),
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// Addresses are GPR 64-bit.
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AArch64::getValueMapping(AArch64::PMI_FirstGPR, 64)}),
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/*NumOperands*/ 2);
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InstructionMapping FPRMapping(
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/*ID*/ 2, /*Cost*/ 1,
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getOperandsMapping(
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{AArch64::getValueMapping(AArch64::PMI_FirstFPR, Size),
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// Addresses are GPR 64-bit.
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AArch64::getValueMapping(AArch64::PMI_FirstGPR, 64)}),
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/*NumOperands*/ 2);
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AltMappings.emplace_back(std::move(GPRMapping));
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AltMappings.emplace_back(std::move(FPRMapping));
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return AltMappings;
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}
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default:
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break;
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}
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return RegisterBankInfo::getInstrAlternativeMappings(MI);
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}
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void AArch64RegisterBankInfo::applyMappingImpl(
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const OperandsMapper &OpdMapper) const {
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switch (OpdMapper.getMI().getOpcode()) {
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case TargetOpcode::G_OR:
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case TargetOpcode::G_BITCAST:
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case TargetOpcode::G_LOAD: {
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// Those ID must match getInstrAlternativeMappings.
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assert((OpdMapper.getInstrMapping().getID() >= 1 &&
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OpdMapper.getInstrMapping().getID() <= 4) &&
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"Don't know how to handle that ID");
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return applyDefaultMapping(OpdMapper);
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}
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default:
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llvm_unreachable("Don't know how to handle that operation");
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}
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}
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/// Returns whether opcode \p Opc is a pre-isel generic floating-point opcode,
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/// having only floating-point operands.
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static bool isPreISelGenericFloatingPointOpcode(unsigned Opc) {
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switch (Opc) {
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case TargetOpcode::G_FADD:
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case TargetOpcode::G_FSUB:
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case TargetOpcode::G_FMUL:
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case TargetOpcode::G_FDIV:
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case TargetOpcode::G_FCONSTANT:
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case TargetOpcode::G_FPEXT:
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case TargetOpcode::G_FPTRUNC:
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return true;
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}
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return false;
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}
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RegisterBankInfo::InstructionMapping
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AArch64RegisterBankInfo::getSameKindOfOperandsMapping(const MachineInstr &MI) {
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const unsigned Opc = MI.getOpcode();
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const MachineFunction &MF = *MI.getParent()->getParent();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned NumOperands = MI.getNumOperands();
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assert(NumOperands <= 3 &&
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"This code is for instructions with 3 or less operands");
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
|
|
unsigned Size = Ty.getSizeInBits();
|
|
bool IsFPR = Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
|
|
|
|
#ifndef NDEBUG
|
|
// Make sure all the operands are using similar size and type.
|
|
// Should probably be checked by the machine verifier.
|
|
// This code won't catch cases where the number of lanes is
|
|
// different between the operands.
|
|
// If we want to go to that level of details, it is probably
|
|
// best to check that the types are the same, period.
|
|
// Currently, we just check that the register banks are the same
|
|
// for each types.
|
|
for (unsigned Idx = 1; Idx != NumOperands; ++Idx) {
|
|
LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());
|
|
assert(AArch64::getRegBankBaseIdxOffset(OpTy.getSizeInBits()) ==
|
|
AArch64::getRegBankBaseIdxOffset(Size) &&
|
|
"Operand has incompatible size");
|
|
bool OpIsFPR = OpTy.isVector() || isPreISelGenericFloatingPointOpcode(Opc);
|
|
(void)OpIsFPR;
|
|
assert(IsFPR == OpIsFPR && "Operand has incompatible type");
|
|
}
|
|
#endif // End NDEBUG.
|
|
|
|
AArch64::PartialMappingIdx RBIdx =
|
|
IsFPR ? AArch64::PMI_FirstFPR : AArch64::PMI_FirstGPR;
|
|
|
|
return InstructionMapping{DefaultMappingID, 1,
|
|
AArch64::getValueMapping(RBIdx, Size), NumOperands};
|
|
}
|
|
|
|
RegisterBankInfo::InstructionMapping
|
|
AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
|
|
const unsigned Opc = MI.getOpcode();
|
|
const MachineFunction &MF = *MI.getParent()->getParent();
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
|
|
// Try the default logic for non-generic instructions that are either copies
|
|
// or already have some operands assigned to banks.
|
|
if (!isPreISelGenericOpcode(Opc)) {
|
|
RegisterBankInfo::InstructionMapping Mapping = getInstrMappingImpl(MI);
|
|
if (Mapping.isValid())
|
|
return Mapping;
|
|
}
|
|
|
|
switch (Opc) {
|
|
// G_{F|S|U}REM are not listed because they are not legal.
|
|
// Arithmetic ops.
|
|
case TargetOpcode::G_ADD:
|
|
case TargetOpcode::G_SUB:
|
|
case TargetOpcode::G_GEP:
|
|
case TargetOpcode::G_MUL:
|
|
case TargetOpcode::G_SDIV:
|
|
case TargetOpcode::G_UDIV:
|
|
// Bitwise ops.
|
|
case TargetOpcode::G_AND:
|
|
case TargetOpcode::G_OR:
|
|
case TargetOpcode::G_XOR:
|
|
// Shifts.
|
|
case TargetOpcode::G_SHL:
|
|
case TargetOpcode::G_LSHR:
|
|
case TargetOpcode::G_ASHR:
|
|
// Floating point ops.
|
|
case TargetOpcode::G_FADD:
|
|
case TargetOpcode::G_FSUB:
|
|
case TargetOpcode::G_FMUL:
|
|
case TargetOpcode::G_FDIV:
|
|
return getSameKindOfOperandsMapping(MI);
|
|
case TargetOpcode::G_BITCAST: {
|
|
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
|
|
LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
|
|
unsigned Size = DstTy.getSizeInBits();
|
|
bool DstIsGPR = !DstTy.isVector();
|
|
bool SrcIsGPR = !SrcTy.isVector();
|
|
const RegisterBank &DstRB =
|
|
DstIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
|
|
const RegisterBank &SrcRB =
|
|
SrcIsGPR ? AArch64::GPRRegBank : AArch64::FPRRegBank;
|
|
return InstructionMapping{DefaultMappingID, copyCost(DstRB, SrcRB, Size),
|
|
AArch64::getCopyMapping(DstIsGPR, SrcIsGPR, Size),
|
|
/*NumOperands*/ 2};
|
|
}
|
|
case TargetOpcode::G_SEQUENCE:
|
|
// FIXME: support this, but the generic code is really not going to do
|
|
// anything sane.
|
|
return InstructionMapping();
|
|
default:
|
|
break;
|
|
}
|
|
|
|
unsigned NumOperands = MI.getNumOperands();
|
|
|
|
// Track the size and bank of each register. We don't do partial mappings.
|
|
SmallVector<unsigned, 4> OpSize(NumOperands);
|
|
SmallVector<AArch64::PartialMappingIdx, 4> OpRegBankIdx(NumOperands);
|
|
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
|
|
auto &MO = MI.getOperand(Idx);
|
|
if (!MO.isReg())
|
|
continue;
|
|
|
|
LLT Ty = MRI.getType(MO.getReg());
|
|
OpSize[Idx] = Ty.getSizeInBits();
|
|
|
|
// As a top-level guess, vectors go in FPRs, scalars and pointers in GPRs.
|
|
// For floating-point instructions, scalars go in FPRs.
|
|
if (Ty.isVector() || isPreISelGenericFloatingPointOpcode(Opc))
|
|
OpRegBankIdx[Idx] = AArch64::PMI_FirstFPR;
|
|
else
|
|
OpRegBankIdx[Idx] = AArch64::PMI_FirstGPR;
|
|
}
|
|
|
|
unsigned Cost = 1;
|
|
// Some of the floating-point instructions have mixed GPR and FPR operands:
|
|
// fine-tune the computed mapping.
|
|
switch (Opc) {
|
|
case TargetOpcode::G_SITOFP:
|
|
case TargetOpcode::G_UITOFP: {
|
|
OpRegBankIdx = {AArch64::PMI_FirstFPR, AArch64::PMI_FirstGPR};
|
|
break;
|
|
}
|
|
case TargetOpcode::G_FPTOSI:
|
|
case TargetOpcode::G_FPTOUI: {
|
|
OpRegBankIdx = {AArch64::PMI_FirstGPR, AArch64::PMI_FirstFPR};
|
|
break;
|
|
}
|
|
case TargetOpcode::G_FCMP: {
|
|
OpRegBankIdx = {AArch64::PMI_FirstGPR,
|
|
/* Predicate */ AArch64::PMI_None, AArch64::PMI_FirstFPR,
|
|
AArch64::PMI_FirstFPR};
|
|
break;
|
|
}
|
|
case TargetOpcode::G_BITCAST: {
|
|
// This is going to be a cross register bank copy and this is expensive.
|
|
if (OpRegBankIdx[0] != OpRegBankIdx[1])
|
|
Cost =
|
|
copyCost(*AArch64::PartMappings[OpRegBankIdx[0]].RegBank,
|
|
*AArch64::PartMappings[OpRegBankIdx[1]].RegBank, OpSize[0]);
|
|
break;
|
|
}
|
|
case TargetOpcode::G_LOAD: {
|
|
// Loading in vector unit is slightly more expensive.
|
|
// This is actually only true for the LD1R and co instructions,
|
|
// but anyway for the fast mode this number does not matter and
|
|
// for the greedy mode the cost of the cross bank copy will
|
|
// offset this number.
|
|
// FIXME: Should be derived from the scheduling model.
|
|
if (OpRegBankIdx[0] >= AArch64::PMI_FirstFPR)
|
|
Cost = 2;
|
|
}
|
|
}
|
|
|
|
// Finally construct the computed mapping.
|
|
RegisterBankInfo::InstructionMapping Mapping =
|
|
InstructionMapping{DefaultMappingID, Cost, nullptr, NumOperands};
|
|
SmallVector<const ValueMapping *, 8> OpdsMapping(NumOperands);
|
|
for (unsigned Idx = 0; Idx < NumOperands; ++Idx)
|
|
if (MI.getOperand(Idx).isReg())
|
|
OpdsMapping[Idx] =
|
|
AArch64::getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]);
|
|
|
|
Mapping.setOperandsMapping(getOperandsMapping(OpdsMapping));
|
|
return Mapping;
|
|
}
|